ST6373 datasheet(49/64 Pages) STMICROELECTRONICS

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ST6373

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SERIAL PERIPHERAL INTERFACE (Cont’d)

SPI Control Register 1 (SCR1)

DDC

Address: EBh - Read/Write

Reset Value: 00h

I C

Address: E5h - Read/Write

Reset Value: 00h

ENA. SPI Enable bit.0 - Disable SPI1 - Enable SPI

Write Only, 0 after Reset.Remark: When the SPI is

disabled, the pins PC0, PC1 and PC3 can be used

as normal I/O pins.

MSS. MASTER/SLAVE Selection (MSS).0 - Se-

lect SLAVE operation1 - Select MASTER opera-

tion

ENIT. Enable SPI Interrupt. The interrupt occurs

on a falling edge of SBOR. In DDC1 Automatic

and in DDC2B Automatic there is an interrupt only

if AUTO has been reset (refer to bit AUTO).

In I2C Slave mode the interrupt occurs at the end

of the address reception only if this address is

matched.

0 = Disable SPI Interrupt

1 = Enable SPI Interrupt

ACKC. Acknowledge Control bit (ACKC). This bit

is used in I

2C reception to control whether not to

send the acknowledge before a RESTART in

MASTER mode, or not to answer if too busy in

SLAVE mode.0 = Enable1 = Disable

Write Only.

This bit is also used in DDC1 mode to change the

polarity of the Acknowledge bit

.0 = Set Acknowledge to high

1 = Set Acknowledge to low

STAG. START Condition Generation for MASTER

2C. [I2C BUS ONLY]0 = No Generation1 = Gener-

ation Start condition

Write Only.

STOG. STOP Condition Generation for MASTER

I2C. [I2C BUS ONLY]0 = No Generation1 = Gener-

ation Stop condition

Write Only.

MS1,MS0. Mode Selection (MS1:MS0).

MS1 is not used for I

2CSPI

Note that NO bit operation instructions are possi-

ble on this register. (SET and RES)

SPI Control Register 2 (SCR2)

DDC

Address: ECh - Read/Write

Reset Value: 00h

I C

Address: E6h - Read/Write

Reset Value: 00h

AUTO. Automatic Operation mode (AUTO). This

bit is automatically reset

:- in DDC1 when SCL goes low

- in DDC2B when no acknowledge is received or

when the data on the SDA line is different from

the one being sent (For example parasitical

STOP or START).

Write Only.

Not used for I2CSPI

INTF. Interrupt Flag (INTF). This flag is set when

an interrupt occurs if enabled. It must be reset be-

fore leaving the interrupt routine.

Read and reset

SCDF. START Condition Detection Flag. This flag

is set on a Start condition detection. It is also set in

DDC1 mode on a high to low transition of SCL. It

must be reset before leaving the interrupt routine.

Read and reset.

BBF. BUSY BUS Flag. (I2C BUS ONLY) Set on a

first START Condition and Reset on the STOP

Condition.

Read and reset.

ENA

MSS

ENIT

ACKC

STAG STOG

MS1

MS0

DDC1 mode with VSYNC as clock [DDC SPI

Only]

Slave Standard Shift [DDC SPI Only]

Master Standard Shift

Multimaster/Slave

2C BUS for DDC2

AUTO

INTF

SCDF

BBF

TRS

VSDAF NADF

SBOR

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