ADIN1300BCPZ-R7 datasheet(15/96 Pages) AD

15 / 96 page

Data Sheet

ADIN1300

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. B | 15 of 96

Table 13. Pin Function Descriptions (Continued)

Pin No.

Mnemonic

Supply Domain Description

PHY Address Hardware Configuration Pin (PHYAD_3).

RXD_2/PHYAD_21

VDDIO

RGMII/MII Receive Data 2 Output (RXD_2). See the MAC Interface section.

PHY Address Hardware Configuration Pin (PHYAD_2).

RXD_1/PHYAD_11

VDDIO

RGMII/RMII/MII Receive Data 1 Output (RXD_1). See the MAC Interface section.

PHY Address Hardware Configuration Pin (PHYAD_1).

RXD_0/PHYAD_01

VDDIO

RGMII/RMII/MII Receive Data 0 Output (RXD_0). See the MAC Interface section.

PHY Address Hardware Configuration Pin (PHYAD_0).

RXC/RX_CLK/

MACIF_SEL01

VDDIO

RGMII Receive Clock Output (RXC). 125 MHz at 1 Gbps, 25 MHz at 100 Mbps, 2.5 MHz at

10 Mbps.

MII Receive Clock Output (RX_CLK). 25 MHz at 100 Mbps, 2.5 MHz at 10 Mbps.

MAC Interface Selection Hardware Configuration Pin (MACIF_SEL0). See Table 27.

RX_CTL/RX_DV/CRS_DV/

MACIF_SEL11

VDDIO

RGMII Receive Control Signal (RX_CTL). This is a combination of the RX_DV and RX_ER signals

using both edges of RXC.

MII Mode Received Data Valid Output (RX_DV). When asserted high, it indicates that valid data is

present on the RXD_0 pin to RXD_3 pin in MII mode.

RMII Mode Carrier Sense/Received Data Valid Signal (CRS_DV). This is a combination of the CRS

and RX_DV signals and is asserted while the receive medium is nonidle. See the RMII Interface

Mode section.

MAC Interface Selection Hardware Configuration Pin (MACIF_SEL1). See Table 27.

TX_CTL/TX_EN

VDDIO

RGMII Transmit Control Signal (TX_CTL). This is a combination of the TX_EN and TX_ER signals

using both edges of TXC.

RMII/MII Mode Transmit Enable Input from the MAC to the PHY (TX_EN). This indicates that

transmission data is available on the TXD_x lines.

TXC/TX_CLK

VDDIO

RGMII Transmit Clock Input (TXC). 125 MHz at 1 Gbps, 25 MHz at 100 Mbps, 2.5 MHz at 10 Mbps

from MAC to PHY.

MII Output Clock from PHY to MAC (TX_CLK). The TX_CLK frequency is 2.5 MHz in 10BASE-Te

mode and 25 MHz in 100BASE-TX mode. TX_CLK has a constant phase relationship to the

XTAL_I/CLK_IN clock.

TXD_0

VDDIO

RGMII/RMII/MII Transmit Data 0 Input. See the MAC Interface section.

LED Interface

LED_0/COL/TX_ER/

PHY_CFG01

AVDD_3P3

Programmable LED Indicator for General-Purpose LED with 8 mA Drive Capability (LED_0).

The LED can be active high or active low. Recommended use is active low. The ADIN1300

automatically senses the connection of the LED during power-up and reset. By default, LED_0 is

on when a link is established and blinking when there is activity (this behavior can be changed by

software).

MII Collision Detect Output (COL). This indicates a collision condition.

MII Transmit Error Detected Input from the MAC to the PHY (TX_ER). Only available by default

when EEE advertisement is enabled using the hardware pin configuration (see Table 25).

4-Level Hardware Configuration Pin for PHY Configuration (PHY_CFG0) (see Table 25).

Other Pins

CLK25_REF

AVDD_3P3

Analog Reference Clock Output. The 25 MHz, 3.3 V reference clock from the crystal oscillator is

available on the CLK25_REF pin.

REXT

AVDD_3P3

External Bias Reference Resistor. Connect a 1% 3.01 kΩ resistor (1% tolerance, 100 ppm/oC

temperature coefficient (TC)) to GND.

LINK_ST/PHY_CFG11

VDDIO

General-Purpose Output Used to Output Link Status (LINK_ST). This indicates whether a valid link

has been established. LINK_ST is active high by default (this can be changed by software).

4-Level Hardware Configuration Pin for PHY Configuration (PHY_CFG1) (see Table 25).

GP_CLK/RX_ER/

MDIX_MODE

General-Purpose Output on which PHY Clocks can be Made Available (GP_CLK).

VDDIO

RMII/MII Mode Receive Error Detected Output (RX_ER). When asserted high, it indicates that the

PHY has detected a receive error.

4-Level Hardware Configuration Pin for Auto-MDIX Configuration (MDIX_MODE). See Table 26.

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