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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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ADIN1300BCPZ-R7 Folha de dados(PDF) 32 Page - Analog Devices |
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ADIN1300BCPZ-R7 Folha de dados(HTML) 32 Page - Analog Devices |
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32 / 96 page  Data Sheet ADIN1300 HARDWARE CONFIGURATION PINS analog.com Rev. B | 32 of 96 PHY Configuration The PHY_CFG1 and PHY_CFG0 hardware configuration pins are shared with the LINK_ST and LED_0 functional pins, respectively. These hardware configuration pins cover the following functions and can be configured according to Table 25: ► Forced/advertised PHY speed ► Software power-down mode after reset ► Downspeed enable ► Energy detect power-down (EDPD) mode ► EEE enable The PHY_CFG1 pin and PHY_CFG0 pin have no internal pull-up resistors, so external resistors must be used to configure these functions. Table 25. PHY Configuration Forced/Advertised PHY Speed Configuration Other Functions Enabled1 LINK_ST/ PHY_CFG1 LED_0/COL/ TX_ER/ PHY_CFG0 Row No. Advertised Speeds (Autonegotiation Enabled) 10 half duplex (HD)/full duplex (FD), 100 HD/FD, and 1000 FD prefer slave Downspeed, EDPD, and EEE MODE_4 MODE_4 1 10 HD/FD, 100 HD/FD, and 1000 FD prefer slave MODE_1 MODE_4 2 10 HD/FD, 100 HD/FD, and 1000 FD prefer master MODE_2 MODE_4 3 10 HD/FD, 100 HD/FD, and 1000 FD prefer slave Software power-down mode after reset MODE_3 MODE_4 4 10 HD/FD and 100 HD/FD MODE_4 MODE_2 5 10 FD and 100 FD MODE_4 MODE_3 6 100 FD and 1000 FD prefer slave MODE_4 MODE_1 7 100 FD and 1000 FD prefer master MODE_3 MODE_1 8 100 FD MODE_1 MODE_1 9 1000 FD prefer slave MODE_2 MODE_1 10 1000 FD prefer master MODE_3 MODE_2 11 Forced Speed (Autonegotiation Disabled) 10 FD MODE_1 MODE_2 12 100 HD MODE_2 MODE_2 13 100 FD MODE_3 MODE_3 14 1 If no function is listed in this column, then only the PHY speed is configured using this row. |
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