ADIN1300BCPZ-R7 datasheet(81/96 Pages) AD

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Data Sheet

ADIN1300

analog.com

Rev. B | 81 of 96

Table 106. Bit Descriptions for B_100_TX_TST_MODE (Continued)

Bits

Bit Name

Description

Reset

Access

[2:0]

B_100_TX_TST_MODE

The PHY provides the ability to transmit a 100BASE-TX test signal that cycles continuously through the

valid MLT3 signal levels: zero, positive, zero, and negative. Each transmit level can be held for either 16

ns (short dwell time) or 112 ns (long dwell time). The MLT3 transmit test waveform with a 16 ns dwell time

measures duty cycle distortion, as specified in Clause 9.1.8 of ANSI Standard X3.263. The MLT3 transmit

test waveform with a 112 ns dwell time measures waveform overshoot, amplitude symmetry, and rise/fall

times, as specified in Clauses 9.1.3, 9.1.4, and 9.1.6 of ANSI Standard X3.263.

0x0

R/W

111: reserved.

110: reserved.

101: reserved.

100: transmit MLT3 test waveform, 112 ns dwell time on Dimension 1.

011: transmit MLT3 test waveform, 112 ns dwell time on Dimension 0.

010: transmit MLT3 test waveform, 16 ns dwell time on Dimension 1.

001: transmit MLT3 test waveform, 16 ns dwell time on Dimension 0.

000: 100BASE-TX test mode disabled.

Low Power Termination Register

Address: 0xB685, Reset: 0x0001, Name: B_100_ZPTM_EN_DIMRX

This register provides the ability to configure for the lowest common-mode impedance on the receive pair for 100BASE-TX.

Table 107. Bit Descriptions for B_100_ZPTM_EN_DIMRX

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

B_100_ZPTM_EN_DIMRX

Applies to 100BASE-TX.

Set to 1 to configure for normal termination on the receive dimension, lowest power (default).

Set to 0 to configure for lowest common mode impedance.

0x1

R/W

Run Automated Cable Diagnostics Register

Address: 0xBA1B, Reset: 0x0000, Name: CDIAG_RUN

This register is used to start the automated running of cable diagnostics and to return results in the cable diagnostic results registers.

Table 108. Bit Descriptions for CDIAG_RUN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

CDIAG_RUN

When set, this bit starts an automatic cable diagnostics run. Run this bit with the PHY in standby. Clear the LINK_EN

bit (PHY_CTRL_3 register, Address 0x0017, Bit 13). This bit self clears when the cable diagnostics are completed.

0x0

R/W

Cable Diagnostics Cross Pair Fault Checking Disable Register

Address: 0xBA1C, Reset: 0x0000, Name: CDIAG_XPAIR_DIS

This register allows the checking of cross pair faults in the cable diagnostics to be disabled.

Table 109. Bit Descriptions for CDIAG_XPAIR_DIS

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

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