ADIN1300BCPZ-R7 datasheet(38/96 Pages) AD

38 / 96 page

Data Sheet

ADIN1300

ON-CHIP DIAGNOSTICS

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Rev. B | 38 of 96

Having enhanced link detection enabled is not suitable for all

applications because it causes the PHY to react quickly to high

levels of disturbance on the MDI lines. This configuration needs to

be considered when performing conformance testing and EMC test-

ing where the media-dependent interface can be exposed to fast

transients. These transients may trigger enhanced link detection to

bring the link down during such tests. In this case, it is preferred to

configure all bits in the FLD_EN register to 0.

START OF PACKET INDICATION

The ADIN1300 includes the detection and indication of the start of

packets (SOP) on the transmit and receive side to support IEEE

1588 time stamp controls and give the MAC more accurate timing

information.

The transmit and receive SOP indication can be made available

at any of the following pins under software configuration: GP_CLK,

LINK_ST, INT_N, and LED_0 using the following override control

registers:

►

GE_IO_GP_CLK_OR_CNTRL bits, Address 0xFF3C

►

GE_IO_GP_OUT_OR_CNTRL bits, Address 0xFF3D

►

GE_IO_INT_N_OR_CNTRL bits, Address 0xFF3E

►

GE_IO_LED_A_OR_CNTRL bits, Address 0xFF40

The detection of the transmit SOP is done after internal PHY FIFO

so there is a fixed delay between the SOP indication at the pin to

the actual SOP at the MDI pins.

Start of packet indication is enabled via the SOP transmit and

receive enables, (set the SOP_TX_EN bit, and the SOP_RX_EN

bit, Address 0x9428).

The SOP is asserted by default on the first byte or nibble of

the frame. The SOP can be configured to be asserted when the

start frame delimitator (SFD) is detected in the frame. This is

configured by setting the SOP SFD enable bit (SOP_SFD_EN,

Address 0x9428).

The SOP indication, by default, is asserted for the duration of the

frame. The SOP can be configured to be asserted for a program-

mable number of cycles. This is configured by setting the SOP

N-cycle enable bit (SOP_NCYC_EN, Address 0x9428), and the

number of cycles in this case is configured via the SOP N by

8 minus 1 cycles register (SOP_N_8_CYC_M_1_D_EN register,

Address 0x9428, Bits[6:4]).

The ADIN1300 start of packet detection and indication circuit in-

cludes the ability to delay each of the SOP transmit and receive in-

dications by a programmable number of clock cycles. The purpose

of this on the receive side is to support MAC interfaces with long

latency so that the received frame SOP indication is not asserted

before the MAC receives the frame. The purpose of this on the

transmit side is to align the transmit SOP indication assertion close

to the reference point set on the MDI pins (so that the time stamp-

ing point does not have to be adjusted at the MAC/switch side).

There are programmable registers for the delays for 1000BASE-T

mode, 100BASE-TX mode, and 10BASE-T mode for transmit and

receive. These are programmed via the SOP_RX_DEL register

and SOP_TX_DEL register, Address 0x9429 and Address 0x942A,

respectively.

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