ADIN1300BCPZ-R7 datasheet(57/96 Pages) AD

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Data Sheet

ADIN1300

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Rev. B | 57 of 96

Table 43. Bit Descriptions for MSTR_SLV_STATUS (Continued)

Bits

Bit Name

Description

Reset

Access

1: local PHY configuration resolved to master.

0: local PHY configuration resolved to slave.

LOC_RCVR_STATUS

Local Receiver Status Bit. Defined by the value of LOC_RCVR_STATUS, as described in Clause 40.4.5.1 of

IEEE Standard 802.3.

0x0

1: local receiver okay (LOC_RCVR_STATUS = okay).

0: local receiver not okay (LOC_RCVR_STATUS = not okay).

REM_RCVR_STATUS

Remote Receiver Status Bit. Defined by the value of REM_RCVR_STATUS as, described in Clause 40.4.5.1

of IEEE Standard 802.3.

0x0

1: remote receiver okay (REM_RCVR_STATUS = okay).

0: remote receiver not okay (REM_RCVR_STATUS = not okay).

LP_FD_1000_ABLE

Link Partner 1000BASE-T Full Duplex Ability Bit. This bit is guaranteed to be valid only when the

PAGE_RX_LAT bit (Register 0x0006, Bit 1) has been set to 1.

0x0

1: link partner is capable of 1000BASE-T full duplex.

0: link partner is not capable of 1000BASE-T full duplex.

LP_HD_1000_ABLE

Link Partner 1000BASE-T Half Duplex Ability Bit. This bit is guaranteed to be valid only when the

PAGE_RX_LAT bit (6.1) has been set to 1.

0x0

1: link partner is capable of 1000BASE-T half duplex.

0: link partner is not capable of 1000BASE-T half duplex.

[9:8]

RESERVED

Reserved.

0x0

[7:0]

IDLE_ERR_CNT

These idle error count bits contain a cumulative count of the errors detected when the receiver is receiving

idles. See Clause 40.5.1.1 of IEEE Standard 802.3 for more details.

0x0

R SC

Extended Status Register

Address: 0x000F, Reset: 0x3000, Name: EXT_STATUS

This address corresponds to the extended status register specified in Clause 22.2.4.4 of IEEE Standard 802.3.

Table 44. Bit Descriptions for EXT_STATUS

Bits

Bit Name

Description

Reset

Access

FD_1000_X_SPRT

This bit is always zero because the PHY does not support full duplex 1000BASE-X.

0x0

HD_1000_X_SPRT

This bit is always zero because the PHY does not support half duplex 1000BASE-X.

0x0

FD_1000_SPRT

This bit is always one because the PHY supports full duplex 1000BASE-T.

0x1

HD_1000_SPRT

This bit is always one because the PHY supports half duplex 1000BASE-T.

0x1

[11:0]

RESERVED

Reserved.

0x0

Extended Register Pointer Register

Address: 0x0010, Reset: 0x0000, Name: EXT_REG_PTR

The extended register pointer and extended register data registers provide a mechanism to access the indirect access address map via directly

accessible registers for cases where the station management does not support Clause 45.

Table 45. Bit Descriptions for EXT_REG_PTR

Bits

Bit Name

Description

Reset

Access

[15:0]

EXT_REG_PTR

The extended register pointer and extended register data registers provide an indirect mechanism to access EMI

registers using normal Clause 22 access for cases where the station management does not support Clause 45.

0x0

R/W

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