ADIN1300BCPZ-R7 datasheet(79/96 Pages) AD

79 / 96 page

Data Sheet

ADIN1300

analog.com

Rev. B | 79 of 96

Table 100. Bit Descriptions for SOP_TX_DEL

Bits

Bit Name

Description

Reset

Access

[15:13]

RESERVED

Reserved.

0x0

[12:8]

SOP_TX_10_DEL_N_8_NS

This bit field specifies the number of 8 ns periods to delay the transmitted frames SOP indication

for 10BASE-T links. To align the transmit SOP indication assertion close to the reference point set

on the MDI pins, set this register to 5'd20.

0x0

R/W

[7:4]

SOP_TX_100_DEL_N_8_NS

This bit field specifies the number of 8 ns periods to delay the transmitted frames SOP indication

for 100BASE-TX links. To align the transmit SOP indication assertion close to the reference point

set on the MDI pins, set this register to 4'd0.

0x0

R/W

[3:0]

SOP_TX_1000_DEL_N_8_NS

This bit field specifies the number of 8 ns periods to delay the transmitted frames SOP indication

for 1000BASE-T links. To align the transmit SOP indication assertion close to the reference

point set on the MDI pins (so that the timestamping point does not have to be adjusted at the

MAC/switch side), set this register to 4'd6.

0x0

R/W

Control of FIFO Depth for MII Modes Register

Address: 0x9602, Reset: 0x0001, Name: DPTH_MII_BYTE

FIFO depth in bytes in MII modes.

Table 101. Bit Descriptions for DPTH_MII_BYTE

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

DPTH_MII_BYTE

Applies to MII modes for 10 Mbps and 100 Mbps. When set, the FIFO depth is in bytes. When zero, the FIFO

depth is in nibbles. The default value of this bit is 1. Therefore, the FIFO prefill is set in bytes. In MII mode,

because the interface is nibble based, the internal prefill in the transmit FIFO is larger and, therefore, the latency

is longer.

0x1

R/W

LPI Wake Error Count Register

Address: 0xA000, Reset: 0x0000, Name: LPI_WAKE_ERR_CNT

This address corresponds to the EEE wake error counter register specified in Clause 45.2.3.10 of IEEE Standard 802.3, which in the IEEE

standard is at MMD Register Address 3.22.

Table 102. Bit Descriptions for LPI_WAKE_ERR_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

LPI_WAKE_ERR_CNT

This bit field counts wake time faults where the PHY fails to complete its normal wake sequence within the

time required. This field self clears upon reading.

0x0

Base 1000 Retrain Enable Register

Address: 0xA001, Reset: 0x0000, Name: B_1000_RTRN_EN

This register allows 1000BASE-T retrain to be enabled. When 1000BASE-T retrain is enabled and the receiver status becomes not okay, the

PHY retrains. During this time, the link remains up but it is not possible to transmit or receive data. When 1000BASE-T retrain is disabled and

the receiver status becomes not okay, the PHY drops the link.

Table 103. Bit Descriptions for B_1000_RTRN_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

B_1000_RTRN_EN

When set, this bit enables 1000BASE-T retrain.

0x0

R/W

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