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ADIN1300BCPZ-R7 Folha de dados(PDF) 70 Page - Analog Devices |
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ADIN1300BCPZ-R7 Folha de dados(HTML) 70 Page - Analog Devices |
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70 / 96 page  Data Sheet ADIN1300 REGISTER SUMMARY analog.com Rev. B | 70 of 96 This register is an indication of signal quality and is a measure of the mean square error on Dimension D. Table 68. Bit Descriptions for MSE_D Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. 0x0 R [7:0] MSE_D This register is an indication of signal quality when a 1000BASE-T link is up and is a measure of the mean square error on Dimension D. 0x0 R Enhanced Link Detection Enable Register Address: 0x8E27, Reset: 0x003D, Name: FLD_EN This register controls the enables for the enhanced link detection function. This is early detection and indication of link loss. Table 69. Bit Descriptions for FLD_EN Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. 0x0 R 7 FLD_PCS_ERR_B_100_EN Enhanced link detection PCS receive error detection enable for 100BASE-TX. 0x0 R/W 6 FLD_PCS_ERR_B_1000_EN Enhanced link detection PCS receive error detection enable for 1000BASE-T. 0x0 R/W 5 FLD_SLCR_OUT_STUCK_B_100_EN Enhanced link detection PMA slicer output stuck at detection enable for 100BASE-TX. 0x1 R/W 4 FLD_SLCR_OUT_STUCK_B_1000_EN Enhanced link detection PMA slicer output stuck at detection enable for 1000BASE-T. 0x1 R/W 3 FLD_SLCR_IN_ZDET_B_100_EN Enhanced link detection PMA slicer input zero detection enable for 100BASE-TX. 0x1 R/W 2 FLD_SLCR_IN_ZDET_B_1000_EN Enhanced link detection PMA slicer input zero detection enable for 1000BASE-T. 0x1 R/W 1 FLD_SLCR_IN_INVLD_B_100_EN Enhanced link detection PMA slicer input invalid level detection enable for 100BASE-TX. Enabled when set high. 0x0 R/W 0 FLD_SLCR_IN_INVLD_B_1000_EN Enhanced link detection PMA slicer input invalid level detection enable for 1000BASE-T. Enabled when set high. 0x1 R/W Enhanced Link Detection Latched Status Register Address: 0x8E38, Reset: 0x0000, Name: FLD_STAT_LAT This register is the latched status for the enhanced link detection function. This bit is latched until the start of the next link-up, when it is cleared. Table 70. Bit Descriptions for FLD_STAT_LAT Bits Bit Name Description Reset Access [15:14] RESERVED Reserved. 0x0 R 13 FAST_LINK_DOWN_LAT Main Enhanced Link Detection Latched Indication. 0x0 R [12:0] RESERVED Reserved. 0x0 R Receive MII Clock Stop Enable Register Address: 0x9400, Reset: 0x0400, Name: RX_MII_CLK_STOP_EN This register contains the clock stop enable bit specified in Clause 45.2.3.1.4 of IEEE Standard 802.3, which, in the IEEE standard, is at MMD Register Address 3.0, Bit 10. Table 71. Bit Descriptions for RX_MII_CLK_STOP_EN Bits Bit Name Description Reset Access [15:11] RESERVED Reserved. 0x0 R |
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