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ADIN1300BCPZ-R7 Folha de dados(PDF) 10 Page - Analog Devices

Nome de Peças ADIN1300BCPZ-R7
Descrição Electrónicos  Robust, Industrial, Low Latency and Low Power 10 Mbps, 100 Mbps, and 1 Gbps Ethernet PHY
PDF  96 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

ADIN1300BCPZ-R7 Folha de dados(HTML) 10 Page - Analog Devices

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Data Sheet
ADIN1300
SPECIFICATIONS
analog.com
Rev. B | 10 of 96
MII Transmit and Receive Timing
Table 5. MII 100BASE-TX Transmit Timing
Parameter
Description
Min
Typ
Max
Unit
t1
TX_CLK period
40
ns
t2
TX_CLK high time
14
20
26
ns
t3
TX_CLK low time
14
20
26
ns
t4
TX_CLK rise/fall time
5
ns
t5
MII input signal (TXD_0 to TXD_3, TX_EN, TX_ER) setup time to TX_CLK
10
ns
t6
MII input signal (TXD_0 to TXD_3, TX_EN, TX_ER) hold time to TX_CLK
0
ns
Figure 5. MII Transmit Timing
Table 6. MII 100BASE-TX Receive Timing
Parameter
Description
Min
Typ
Max
Unit
t1
RX_CLK period
40
ns
t2
RX_CLK high time
16
20
24
ns
t3
RX_CLK low time
16
20
24
ns
t4
RX_CLK rise/fall time
1
ns
t5
MII output signal (RXD_0 to RXD_3, RX_DV, RX_ER) setup time to RX_CLK
10
ns
t6
MII output signal (RXD_0 to RXD_3, RX_DV, RX_ER) hold time to RX_CLK
10
ns
Figure 6. MII Receive Timing
Table 7. MII 10BASE-Te Transmit Timing (See Figure 5)
Parameter
Description
Min
Typ
Max
Unit
t1
TX_CLK period
400
ns
t2
TX_CLK high time
140
200
260
ns
t3
TX_CLK low time
140
200
260
ns
t4
TX_CLK rise/fall time
1
ns
t5
MII input signal (TXD_0 to TXD_3, TX_EN, TX_ER) setup time to TX_CLK
10
ns
t6
MII input signal (TXD_0 to TXD_3, TX_EN, TX_ER) hold time to TX_CLK
0
ns
Table 8. MII 10BASE-Te Receive Timing (See Figure 6)
Parameter
Description
Min
Typ
Max
Unit
t1
RX_CLK period
400
ns
t2
RX_CLK high time
140
200
260
ns



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