ADIN1300BCPZ-R7 datasheet(58/96 Pages) AD

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Data Sheet

ADIN1300

analog.com

Rev. B | 58 of 96

Table 45. Bit Descriptions for EXT_REG_PTR (Continued)

Bits

Bit Name

Description

Reset

Access

Write the 16-bit register address into the EXT_REG_PTR register. The EMI register can be read or written by

reading or writing the EXT_REG_DATA register. An EMI register can be directly accessed using Clause 45 access.

Extended Register Data Register

Address: 0x0011, Reset: 0x0000, Name: EXT_REG_DATA

The extended register pointer and extended register data registers provide a mechanism to access the indirect access address map via directly

accessible registers for cases where the station management does not support Clause 45.

Table 46. Bit Descriptions for EXT_REG_DATA

Bits

Bit Name

Description

Reset

Access

[15:0]

EXT_REG_DATA

The extended register pointer and extended register data registers provide an indirect mechanism to access EMI

registers using normal Clause 22 access for cases where the station management does not support Clause 45.

See Table 45 for further details.

0x0

R/W

PHY Control 1 Register

Address: 0x0012, Reset: 0x0002, Name: PHY_CTRL_1

This register provides access to various PHY control register bits, in particular for diagnostic clocking control and MDI crossover.

Table 47. Bit Descriptions for PHY_CTRL_1

Bits

Bit Name

Description

Reset

Access

[15:11]

RESERVED

Reserved.

0x0

AUTO_MDI_EN

The automatic MDI/MDIX resolution enable register bit allows the automatic cable crossover feature of the PHY

to be controlled. Note that the default value of this register bit is configurable via a hardware configuration pin,

which allows the default operation of the PHY to be configured in unmanaged applications.

0x0

R/W

1: enable auto MDI/MDIX. Prefer MDI if MAN_MDIX is 1'b0 and prefer MDIX if MAN_MDIX is 1'b1.

0: disable auto MDI/MDIX.

MAN_MDIX

When this bit is set and the AUTO_MDI_EN bit is clear, the PHY operates in the MDIX configuration. In this

configuration, no crossover is implemented and the logical pairs of the PCS correspond to the physical pairs of

the AFE. When this bit is clear and the AUTO_MDI_EN bit is clear, the PHY operates in the MDI configuration

and crossovers the pairs. If the AUTO_MDI_EN bit is set, the MAN_MDIX bit determines the MDI or MDIX

preference option.

0x0

R/W

1: operate in MDIX configuration.

0: operate in MDI configuration.

[8:3]

RESERVED

Reserved.

0x0

DIAG_CLK_EN

Enable PHY Diagnostics Clock. This clock is required for certain diagnostic functions within the PHY, for example,

the frame generator/checker.

0x0

R/W

1: enable PHY diagnostics clock.

0: disable PHY diagnostics clock.

[1:0]

RESERVED

Reserved.

0x2

R/W

PHY Control Status 1 Register

Address: 0x0013, Reset: 0x1041, Name: PHY_CTRL_STATUS_1

This register provides access to PHY loopback control bits.

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