ADIN1300BCPZ-R7 datasheet(71/96 Pages) AD

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Data Sheet

ADIN1300

analog.com

Rev. B | 71 of 96

Table 71. Bit Descriptions for RX_MII_CLK_STOP_EN (Continued)

Bits

Bit Name

Description

Reset

Access

RX_MII_CLK_STOP_EN

If this bit is set, the PHY may stop the receive MII clock while it is signaling low power enable (LPI).

Otherwise, it keeps the clock active.

0x1

R/W

1: the PHY may stop the clock during LPI.

0: clock not stoppable.

[9:0]

RESERVED

Reserved.

0x0

PCS Status 1 Register

Address: 0x9401, Reset: 0x0040, Name: PCS_STATUS_1

The bits contained in this register correspond to the bits in the PCS Status 1 register specified in Clause 45.2.3.2 of IEEE Standard 802.3,

which, in the IEEE standard, is at MMD Register Address 3.1, Bits[11:8] and Bit 6.

Table 72. Bit Descriptions for PCS_STATUS_1

Bits

Bit Name

Description

Reset

Access

[15:12]

RESERVED

Reserved.

0x0

TX_LPI_RCVD

The transmit LPI received bit is a latched version of TX_LPI. When this bit goes high, it latches high

until it is unlatched by reading.

0x0

1: transmit PCS has received LPI.

0: LPI not received.

RX_LPI_RCVD

The receive LPI received bit is a latched version of RX_LPI. When this bit goes high, it latches high

until it is unlatched by reading.

0x0

1: receive PCS has received LPI.

0: LPI not received.

TX_LPI

Transmit LPI Bit.

0x0

1: transmit PCS is currently receiving LPI.

0: PCS is not currently receiving LPI.

RX_LPI

Receive LPI Bit.

0x0

1: receive PCS is currently receiving LPI.

0: PCS is not currently receiving LPI.

RESERVED

Reserved.

0x0

TX_MII_CLK_STOP_CPBL

The transmit MII clock stop capable bit always reads as 1'b1.

0x1

1: the MAC may stop the clock during LPI.

0: clock not stoppable.

[5:0]

RESERVED

Reserved.

0x0

Frame Checker Enable Register

Address: 0x9403, Reset: 0x0001, Name: FC_EN

This register is used to enable the frame checker. The frame checker analyzes the received frames from either the MAC interface or the PHY

(see the FC_TX_SEL register, Address 0x9407, Bit 0) to report the number of frames received, CRC errors, and various other frame errors. The

frame checker frame and error counter registers count these events.

Table 73. Bit Descriptions for FC_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

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