TPS6521825_V01 datasheet(98/109 Pages) TI1

98 / 109 page

Thermal

Pad

Via to Ground Plane

Via to Internal Plane

Input Bypass

Capacitor

Output Filter

Capacitor

VOUT

TPS6521825

SLDS260 – NOVEMBER 2019

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Layout

Power Supply Recommendations

The device is designed to operate with an input voltage supply range between 2.7 V and 5.5 V. This input

supply can be from a single cell Li-Ion battery or other externally regulated supply. If the input supply is

located more than a few inches from the TPS6521825 additional bulk capacitance may be required in

addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 47 µF is a typical

choice.

The coin cell back up input is designed to operate with a input voltage supply between 2.2 V and 3.3 V

This input should be supplied by a coin cell battery with 3-V nominal voltage.

Layout

8.1

Layout Guidelines

Follow these layout guidelines:

•

The IN_X pins should be bypassed to ground with a low ESR ceramic bypass capacitor. The typical

recommended bypass capacitance is 4.7-µF with a X5R or X7R dielectric.

•

The optimum placement is closest to the IN_X pins of the device. Take care to minimize the loop area

formed by the bypass capacitor connection, the IN_X pin, and the thermal pad of the device.

•

The thermal pad should be tied to the PCB ground plane with a minimum of 25 vias. See Figure 8-2 for

an example.

•

The LX trace should be kept on the PCB top layer and free of any vias.

•

The FBX traces should be routed away from any potential noise source to avoid coupling.

•

DCDC4 Output capacitance should be placed immediately at the DCDC4 pin. Excessive distance

between the capacitance and DCDC4 pin may cause poor converter performance.

8.2

Layout Example

Figure 8-1. Layout Recommendation

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