TPS6521825_V01 datasheet(45/109 Pages) TI1

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From master to slave

R Read (high)

W Write (low)

S Start

P Stop

From slave to master

A Acknowledge

A Not Acknowledge

SLAVE ADDRESS

DATAREGADDR

DATASUBADDR+n+1

DATASUBADDR+n

DATAREGADDR+n+1

DATAREGADDR+n

SLAVE ADDRESS

n bytes + ACK

A0 R/nW

R/nW

...

Slave Address + R/nW

Data

Subaddress

Device Address

Acknowledge

Stop Condition

Start Condition

Read, Not Write

TPS6521825

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SLDS260 – NOVEMBER 2019

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Product Folder Links: TPS6521825

Detailed Description

(1)

Note: The SCL duty cycle at 400 kHz must be >40%.

5.3.1.18 I2C Bus Operation

The TPS6521825 hosts a slave I2C interface (address 0x24) that supports data rates up to 400 kbps,

auto-increment addressing. (1)

Figure 5-30. Subaddress in I2C Transmission

The I2C bus is a communications link between a controller and a series of slave terminals. The link is

established using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA).

The serial clock is sourced from the controller in all cases where the serial data line is bi-directional for

data communication between the controller and the slave terminals. Each device has an open drain output

to transmit data on the serial data line. An external pullup resistor must be placed on the serial data line to

pull the drain output high during data transmission.

Data transmission initiates with a start bit from the controller as shown in Figure 5-32. The start condition

is recognized when the SDA line transitions from high to low during the high portion of the SCL signal.

Upon reception of a start bit, the device receives serial data on the SDA input and checks for valid

address and control information. If the appropriate slave address is set for the device, the device issues

an acknowledge pulse and prepares to receive register address and data. Data transmission is completed

by either the reception of a stop condition or the reception of the data word sent to the device. A stop

condition is recognized as a low to high transition of the SDA input during the high portion of the SCL

signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An

acknowledge issues after the reception of valid slave address, register-address, and data words. The I2C

interfaces an auto-sequence through the register addresses, so that multiple data words can be sent for a

given I2C transmission. Reference Figure 5-31 and Figure 5-32 for details.

Top: Master Writes Data to Slave

Bottom: Master Reads Data from Slave

Figure 5-31. I2C Data Protocol

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