TPS6521825_V01 datasheet(44/109 Pages) TI1

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INT pin (output)

AC_STATE bit

2C access to INT register

AC_DET pin

(10-ms deglitched input)

AC goes low, INT

pin is pulled low,

PC_STATE bit is

set.

INT register is read

through I

2C while AC

remains low. INT pin is

released, AC_STATE bit

remains set.

AC goes high. INT

pin is pulled low,

AC_STATE bit is

reset.

INT register is read

through I

2C. INT pin is

released.

AC goes low, INT

pin is pulled low,

AC_STATE bit is

set.

AC goes high before

INT register is read

through I

2C. INT pin

remains low,

AC_STATE bit is reset.

INT register is read

through I

2C.

AC interrupt bit

TPS6521825

SLDS260 – NOVEMBER 2019

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Detailed Description

In ACTIVE state, the TPS6521825 monitors the AC_DET input and issues an interrupt when the pin status

changes, such as when it drops below or rises above the AC_DET input-low or input-high thresholds. The

interrupt is masked by the ACM bit in the INT_MASK1 register.

Figure 5-29. AC_STATE Pin

NOTE

Interrupts are issued whenever the AC_DET pin status changes. The AC_STATE bit reflects

the current status of the AC_DET input.

5.3.1.17 Interrupt Pin (INT)

The interrupt pin signals any event or fault condition to the host processor. Whenever a fault or event

occurs in the device, the corresponding interrupt bit is set in the INT register, and the open-drain output is

pulled low. The INT pin is released (returns to Hi-Z state) and fault bits are cleared when the host reads

the INT register. If a failure persists, the corresponding INT bit remains set and the INT pin is pulled low

again after a maximum of 32 µs.

The MASK register masks events from generating interrupts. The MASK settings affect the INT pin only,

and have no impact on the protection and monitor circuits.

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