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TPS6521825 Folha de dados(PDF) 53 Page - Texas Instruments |
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TPS6521825 Folha de dados(HTML) 53 Page - Texas Instruments |
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53 / 109 page ![]() 53 TPS6521825 www.ti.com SLDS260 – NOVEMBER 2019 Submit Documentation Feedback Product Folder Links: TPS6521825 Detailed Description Copyright © 2019, Texas Instruments Incorporated 5.6.4.2 INT1 Register (subaddress = 0x01) [reset = 0x00] INT1 is shown in Figure 5-37 and described in Table 5-9. Return to Summary Table. Figure 5-37. INT1 Register 7 6 5 4 3 2 1 0 RESERVED VPRG AC PB HOT CC_AQC PRGC R-00b R-0b R-0b R-0b R-0b R-0b R-0b Table 5-9. INT1 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 00b 5 VPRG R 0b Programming voltage interrupt: 0b = No significance. 1b = Input voltage is too low for programming power-up default values. 4 AC R 0b AC_DET pin status change interrupt. Note: Status information is available in STATUS register. 0b = No change in status. 1b = AC_DET status change (AC_DET pin changed high to low or low to high). 3 PB R 0b Push-button status change interrupt. Note: Status information is available in STATUS register 0b = No change in status. 1b = Push-button status change (PB changed high to low or low to high). 2 HOT R 0b Thermal shutdown early warning: 0b = Chip temperature is below HOT threshold. 1b = Chip temperature exceeds HOT threshold. 1 CC_AQC R 0b Coin cell battery voltage acquisition complete interrupt: 0b = No significance. 1b = Backup battery status comparators have settled and results are available in STATUS register. 0 PRGC R 0b EEPROM programming complete interrupt: 0b = No significance. 1b = Programming of power-up default settings has completed successfully. |
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