TPS6521825_V01 datasheet(34/109 Pages) TI1

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VIN_BIAS

UVLO (internal signal)

UVLO active

UVLO inactive

UVLO threshold, supply falling

< 5 ms

> 5-ms

deglitch

UVLO hysteresis

TPS6521825

SLDS260 – NOVEMBER 2019

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Detailed Description

If the slew rate of the IN_BIAS voltage is less than 30 V/s, then TPS6521825 will power up at VULVO +

VHYS. Once the input voltage rises above this level, the input voltage may drop to the VUVLO level before

the PMIC shuts down. In this scenario, if the input voltage were to fall below VUVLO but above 2.5 V, the

input voltage would have to recover above VUVLO + VHYS in less than 5 ms for the device to remain active.

In either slew rate scenario, if the input voltage were to fall below 2.5 V, the digital core is reset and all

remaining power rails are shut down instantaneously and are pulled low to ground by their internal

discharge circuitry (DCDC1-4 and LDO1).

Figure 5-15. Definition of UVLO and Hysteresis

After the UVLO triggers, the internal LDO blocks current flow from its output capacitor back to the IN_BIAS

pin, allowing the digital core and the discharge circuits to remain powered for a limited amount of time to

properly shut-down and discharge the output rails. The hold-up time is determined by the value of the

capacitor connected to INT_LDO. See Section 5.3.1.6 for more details.

TPS6521825 Folha de dados(PDF) 34 Page - Texas Instruments