TPS6521825_V01 datasheet(31/109 Pages) TI1

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SOC

From DCDC3

LS1_I

LS1_EN

LS1nPFO

LS1DIS

LS1_F

IN_LS1

LS1

250

10 …F

DDR Memory

Interface

TPS6521825

www.ti.com

SLDS260 – NOVEMBER 2019

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Detailed Description

5.3.1.7

Current Limited Load Switches

The TPS6521825 provides three current limited load switches with individual inputs, outputs, and enable

control. Each switch provides the following control and diagnostic features:

•

The ON or OFF state of the switch is controlled by the corresponding LSx_EN bit in the ENABLE

•

LS1 can be controlled by the sequencer or through I2C communication.

•

LS2 and LS3 can only be controlled through I2C communication. The sequencer has no control over

LS2 and LS3.

•

Each switch has an active discharge function, disabled by default, and enabled through the

LSxDCHRG bit. When enabled, the switch output is discharged to ground whenever the switch is

disabled.

•

When the PFI input drops below the power-fail threshold (the power-fail comparator trips), the load

switches are automatically disabled to shed system load. This function must be individually enabled for

each switch through the corresponding LSxnPFO bit. The switches do not turn back on automatically

as the system voltage recovers, and must be manually re-enabled.

•

An interrupt (LSx_I) issues whenever a load switch actively limits the output current, such as when the

output load exceeds the current limit value. The switch remains ON and provides current to the load

according to the current-limit setting.

•

All three load switches have local overtemperature sensors which disable the corresponding switch if

the power dissipation and junction temperature exceeds the safe operating value. The switch

automatically recovers once the temperature drops below the OTS threshold value minus hysteresis.

The LSx_F (fault) interrupt bit is set while the switch is held OFF by the OTS function.

5.3.1.7.1 Load Switch 1 (LS1)

LS1 is a non-reverse blocking, low-voltage (< 3.6 V), low-impedance switch intended to support DDRx

self-refresh mode by cutting off the DDRx supply to the SOC DDRx interface during SUSPEND mode. In a

typical application, the input of LS1 is tied to the output of DCDC3 while the output of LS1 is connected to

the memory-interface supply pin of the SOC. LS1 can be controlled by the internal sequencer, just as any

power rail.

Figure 5-11. Typical Application of Load Switch 1

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