TPS6521825_V01 datasheet(39/109 Pages) TI1

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GPIO1

GPO1 (user register bit, sequencer control enabled)

DCDC 1 and DCDC 2 reset

GPO2

GPO2 (user register bit)

IO1_SEL (EEPROM: 0b = output, 1b = input)

IN_LS1

PGOOD (1 ms delayed)

GPO2_BUF (EEPROM: 0b = open drain, 1b = push-pull)

GPO3 (user register bit, sequencer control enabled)

DC12_RST (EEPROM: 0b = disabled, 1b = enabled)

Latch,

Gating

GPIO3

GPO2

IN_LS1

Push-Pull

Driver

Open-Drain

Driver

External

pullup supply

Leakage path if external

pullup supply is > IN_LS1

TPS6521825

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SLDS260 – NOVEMBER 2019

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Detailed Description

Figure 5-22. GPO2 as Open-Drain Output

NOTE

When configured as open-drain output, the external pull-up supply must not exceed the

voltage level on IN_LS1 pin.

5.3.1.14.2 Using GPIO3 as Reset Signal to DCDC1 and DCDC2

The GPIO3 is an edge-sensitive reset input to the PMIC, when the DC12_RST bit set to 1. The reset

signal affects DCDC1 and DCDC2 only, so that only those two registers are reset to the power-up default

whenever GPIO3 input transitions from high to low, while all other registers maintain their current values.

DCDC1 and DCDC2 transition back to the default value following the SLEW settings, and are not power

cycled. This function recovers the processor from reset events while in low-power mode.

Figure 5-23. I/O Pin Logic

TPS6521825 Folha de dados(PDF) 39 Page - Texas Instruments