TPS6521825_V01 datasheet(28/109 Pages) TI1

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DCDC2

PWR_EN

(deglitched)

PG DCDC3

(internal)

DCDC1

DCDC4

PG DCDC4

(internal)

VSYS

DCDC3

PG DCDC2

(internal)

PG DCDC1

(internal)

LDO1

PG LDO1

(internal)

5 ms

PGOOD

PG_DLY

5 ms

DLY3 + DLY4

DLY5 + DLY6

DLY9

DLY7

DLY6 + DLY5

FAULT

DLY8

nWAKEUP

5 s (maximum)

DLY7

DLY4 + DLY3

DLY1 + DLY2

5 ms

TPS6521825

SLDS260 – NOVEMBER 2019

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Detailed Description

•

Disabling a rail manually by resetting the DCx_EN or LDO1_EN bit has no effect on the PGOOD pin. If

all rails are disabled, the PGOOD is driven low as the last rail is disabled.

•

If the power-down sequencer is triggered, PGOOD is driven low.

•

The PGOOD is driven low in the SUSPEND state, regardless of the number of rails that are enabled.

Figure 5-8 shows a typical power-up sequence and PGOOD timing.

(1)

Sequence shown for TPS65218D0 variant. For other TPS65218xx variants, refer to registers SEQ1-7 in Section 5.6.4 for factory-

programmed sequence order and timing.

Figure 5-8. Typical Power-Up Sequence of the Main Output Rails for TPS65218D0

5.3.1.5

Backup Supply Power-Good (PGOOD_BU)

PGOOD_BU is a push-pull output indicating if DCDC5 and DCDC6 are in regulation. The output is driven

to high when both rails are in regulation, and driven low if at least one of the rails is below the power-good

threshold. The output-high level is equal to the output voltage of DCDC6.

PGOOD_BU is the logical and between PGOOD (DCDC5) and PGOOD (DCDC6), and has no delay time

built-in. Unlike the main power-good, a fault on DCDC5 or DCDC6 does not trigger the power-down

sequencer, does not disable any of the rails in the system, and has no effect on the PGOOD pin. DCDC5

and DCDC6 recover automatically once the fault is removed.

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