TPS6521825_V01 datasheet(33/109 Pages) TI1

33 / 109 page

Enable 100-k

load resistor on CC

input.

Enable comparators.

Wait 600 ms

Latch comparator outputs;

Store result in CC_STAT[1:0]

DISABLED

CC_AQ = 1

Disable 100-k

load resistor.

Disable comparators

Restore CC_AQ bit to 0 (CC_AQ = 0)

Issue interrupt (CC_AQC = 1)

CC_STAT[1:0] = 00b ± VCC < VLOW; Coin cell is not present or at end-of-life (EOL).

CC_STAT[1:0] = 01b ± VLOW < VCC < VGOOD; Coin cell is LOW.

CC_STAT[1:0] = 10b ± VGOOD < VCC < VIDEAL; Coin cell is GOOD.

CC_STAT[1:0] = 11b ± VIDEAL < VCC; Coin cell voltage is IDEAL.

LOAD ENABLE

Coin Cell

VREF

LOW (2.3 V)

GOOD (2.6 V)

VREF

IDEAL (3 V)

CC_STAT[1:0]

LOGIC CORE

TPS6521825

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SLDS260 – NOVEMBER 2019

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Product Folder Links: TPS6521825

Detailed Description

5.3.1.8

LDO1

LDO1 is a general-purpose LDO intended to provide power to analog circuitry on the SOC. LDO1 has an

input voltage range from 1.8 V to 5.5 V, and can be connected either directly to the system power or the

output of a DCDC converter. The output voltage is programmable in the range of 0.9 V to 3.4 V with a

default of 1.8 V. LDO1 supports up to 200 mA at the minimum specified headroom voltage, and up to 400

mA at the typical operating condition of VOUT = 1.8 V, VIN_LDO1 > 2.7 V.

5.3.1.9

Coin Cell Battery Voltage Acquisition

Figure 5-14. Left: Flow Chart for Acquiring Coin Cell Battery Voltage

Right: Comparator Circuit

5.3.1.10 UVLO

Depending on the slew rate of the input voltage into the IN_BIAS pin, the power rails of TPS6521825 will

be enabled at either VULVO or VULVO + VHYS.

If the slew rate of the IN_BIAS voltage is greater than 30 V/s, then TPS6521825 will power up at VULVO.

Once the input voltage rises above this level, the input voltage may drop to the VUVLO level before the

PMIC shuts down. In this scenario, if the input voltage were to fall below VUVLO but above 2.55 V, the input

voltage would have to recover above VUVLO in less than 5 ms for the device to remain active.

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