TPS6521825_V01 datasheet(29/109 Pages) TI1

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PWR_EN

(deglitched)

PG DCDC6

(internal)

VSYS

DCDC6

DCDC5

PG DCDC5

(internal)

PGOOD_BU

DLY1

nWAKEUP

5 s (maximum)

TPS6521825

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SLDS260 – NOVEMBER 2019

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Detailed Description

NOTE

In this example, the power-down is triggered by a fault on DCDC3.

This timing diagram assumes each rail powers up within the strobe delay time. If a rail takes

longer than the strobe delay time to power up, the next rail will wait for the previous rail to

reach its PGOOD voltage, and then may wait an additional 1 ms until it is enabled.

(1)

Sequence shown for TPS65218D0 and TPS6521825 variants. For TPS6521815 variant, order and timing of DCDC5 and DCDC6 can

be modified using registers SEQ1-2 and SEQ5 in Section 5.6.4.

Figure 5-9. Typical Power-Up Sequence of DCDC5 and DCDC6

5.3.1.6

Internal LDO (INT_LDO)

The internal LDO provides a regulated voltage to the internal digital core and analog circuitry. The internal

LDO has a nominal output voltage of 2.5 V and can support up to 10 mA of external load. During

EEPROM programming, the output voltage is elevated to 3.6 V as described in Section 5.5.1. Therefore,

any external circuitry connected to INT_LDO must be capable of supporting that voltage.

When system power fails, the UVLO comparator triggers the power-down sequence. If system power

drops below 2.3 V, the digital core is reset and all remaining power rails are shut down instantaneously

and are pulled low to ground by their internal discharge circuitry (DCDC1-4 and LDO1).

The internal LDO reverse blocks to prevent the discharging of the output capacitor (CINT_LDO) on the

INT_LDO pin. The remaining charge on the INT_LDO output capacitor provides a supply for the power rail

discharge circuitry to ensure the outputs are discharged to ground even if the system supply has failed.

The amount of hold-up time specified in Section 4.5 is a function of the output capacitor value (CINT_LDO)

and the amount of external load on the INT_LDO pin, if any. The design allows for enough hold-up time to

sufficiently discharge DCDC1-4, and LDO1 to ensure proper processor power-down sequencing.

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