ADP1055ACPZ-R7 datasheet(123/140 Pages) AD

123 / 140 page

Data Sheet

ADP1055

Rev. A | Page 123 of 140

Table 226. Register 0xFE8F—FAULT_TEMPERATURE

Bits

Bit Name

R/W

Description

[7:0]

FAULT_TEMPERATURE

Unlatched fault conditions after debounce (see STATUS_TEMPERATURE for latched version)

Table 227. Register 0xFE90—FAULT_CML

Bits

Bit Name

R/W

Description

[7:0]

FAULT_CML

Unlatched fault conditions after debounce (see STATUS_CML for latched version)

Table 228. Register 0xFE91—FAULT_OTHER

Bits

Bit Name

R/W

Description

[7:0]

FAULT_OTHER

Unlatched fault conditions after debounce (see STATUS_OTHER for latched version)

Table 229. Register 0xFE92—FAULT_MFR_SPECIFIC

Bits

Bit Name

R/W

Description

[7:0]

FAULT_MFR_SPECIFIC

Unlatched fault conditions after debounce (see STATUS_MFR_SPECIFIC for latched version)

Table 230. Register 0xFE93—FAULT_UNKNOWN

Bits

Bit Name

R/W

Description

[15:0]

FAULT_UNKNOWN

Unlatched fault conditions after debounce (see STATUS_UNKNOWN for latched version)

Table 231. Register 0xFE94—STATUS_UNKNOWN

Bits

Bit Name

R/W

Description

EEPROM unlocked

R/W

The EEPROM is unlocked.

Adaptive dead time

R/W

Adaptive dead time threshold has been crossed.

Soft start filter

R/W

The soft start filter is in use.

Soft start ramp

or soft stop ramp

R/W

The reference is being ramped up (soft start) or ramped down (soft stop).

Modulation limit

R/W

Modulation is at its minimum or maximum limit.

Volt-second and

duty balance limit

R/W

Volt-second balance or duty balance at is the maximum/minimum limit.

Light load mode

R/W

The device is in light load mode.

Constant current

R/W

Power supply is operating in constant current mode (constant current mode is enabled).

PGOOD2 fault

R/W

PGOOD2 fault. At least one of the flags listed in Register 0xFE45 has been set (see Table 182).

PGOOD1 fault

R/W

PGOOD1 fault. At least one of the flags listed in Register 0xFE44 has been set (see Table 181).

Sync unlock

R/W

Sync mode is enabled, but unit not locked to sync input frequency.

SR off

R/W

Synchronous rectifiers SR1 and SR2 are disabled. This flag is set when one of the following cases

is true: SR1 and SR2 are disabled by the user; the load current has fallen below the threshold in

rectifiers; or SR outputs are blanked during soft start and during a pulse skip condition.

Address warning

R/W

I2C/PMBus address warning. ADD resistor value out-of-range.

VCORE OV

R/W

2.5 V VCORE is above limit. Action is set to immediate shutdown.

VDD OV

R/W

VDD is above limit. The I2C interface stays functional, but a unit power-off/power-on sequence

is required to restart the power supply. The response to a VDD overvoltage is programmable in

VDD UV

R/W

VDD is below limit. The response to a VDD undervoltage immediate shutdown.

ADP1055ACPZ-R7 Folha de dados(PDF) 123 Page - Analog Devices

ADP1055ACPZ-R7 Folha de dados(HTML) 123 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL