ADP1055ACPZ-R7 datasheet(86/140 Pages) AD

86 / 140 page

ADP1055

Data Sheet

Rev. A | Page 86 of 140

MANUFACTURER SPECIFIC PMBUS COMMAND DESCRIPTIONS

Table 127. Register 0xFE00—GO_CMD

Bits

Bit Name

R/W

Description

Reserved

R/W

Reserved.

SYNC

This bit latches Register 0xFE55.

VFF

This bit latches Register 0xFE29.

Double update rate,

VS balance

This bit latches Register 0xFE57 and Register 0xFE25.

Filter GO

This bit latches Register 0xFE4A, Register 0xFE01 to Register 0xFE0C, Register 0xFE5E, and

Frequency GO

Update switching frequency programmed by FREQUENCY_SWITCH command

(Register 0x33).

PWM GO

Update Register 0xFE0D to Register 0xFE1C, Register 0xFE1F to Register 0xFE24, and

Voltage reference GO

Update reference voltage commanded by the VOUT_COMMAND (Register 0x21).

Figure 85. Digital Filter Programmability

Table 128. Register 0xFE01—NM_DIGFILT_LF_GAIN_SETTING (Requires Use of the GO Bit in Register 0xFE00)

Bits

Bit Name

R/W

Description

[7:0]

LF gain setting

R/W

This register determines the low frequency gain of the loop response in normal mode. It is

programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 85.

Table 129. Register 0xFE02—NM_DIGFILT_ZERO_SETTING (Requires Use of the GO Bit in Register 0xFE00)

Bits

Bit Name

R/W

Description

[7:0]

Zero setting

R/W

This register determines the position of the final zero in normal mode. See Figure 85.

Table 130. Register 0xFE03—NM_DIGFILT_POLE_SETTING (Requires Use of the GO Bit in Register 0xFE00)

Bits

Bit Name

R/W

Description

[7:0]

Pole setting

R/W

This register determines the position of the final pole in normal mode. See Figure 85.

Table 131. Register 0xFE04—NM_DIGFILT_HF_GAIN_SETTING (Requires Use of the GO Bit in Register 0xFE00)

Bits

Bit Name

R/W

Description

[7:0]

HF gain setting

R/W

This register determines the high frequency gain of the loop response in normal mode. It is

programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 85.

Table 132. Register 0xFE05—LLM_DIGFILT_LF_GAIN_SETTING (Requires Use of the GO Bit in Register 0xFE00)

Bits

Bit Name

R/W

Description

[7:0]

LF gain setting

R/W

This register determines the low frequency gain of the loop response in light load mode. It is

programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 85.

POLE LOCATION RANGE

ZERO

POLE

100Hz

500Hz

1kHz

5kHz

10kHz

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