ADP1055ACPZ-R7 datasheet(53/140 Pages) AD

53 / 140 page

Data Sheet

ADP1055

Rev. A | Page 53 of 140

LAYOUT GUIDELINES

This section describes best practices to ensure optimal performance

of the ADP1055. In general, place all components as close to the

ADP1055 as possible. All signals should be referenced to their

respective grounds.

CS2+ AND CS2− PINS

Route the traces from the sense resistor to the ADP1055 parallel

to each other. Keep the traces close together and as far from the

switch nodes as possible.

VS+ AND VS− PINS

Route the traces from the remote voltage sense point to the

ADP1055 parallel to each other. Keep the traces close together

and as far from the switch nodes as possible. Place a 100 nF

capacitor from VS− to AGND to reduce common-mode noise.

VDD PIN

Place decoupling capacitors as close to the device as possible. A

4.7 μF capacitor from VDD to AGND is recommended.

SDA AND SCL PINS

Route the traces to the SDA and SCL pins parallel to each other.

Keep the traces close together and as far from the switch nodes

as possible. It may be advantageous to add a filtering circuit, as

shown in Figure 81.

Figure 81. I2C Filtering Circuit

CS1 PIN

Route the traces from the current sense transformer to

the ADP1055 parallel to each other. Keep the traces close

together and as far from the switch nodes as possible.

EXPOSED PAD

Solder the exposed thermal pad on the underside of the ADP1055

package to the PCB AGND plane.

VCORE PIN

Place a 330 nF decoupling capacitor from the VCORE pin to

DGND, as close to the device as possible.

RES PIN

Place a 10 kΩ, 0.1% resistor from the RES pin to AGND, as

close to the device as possible.

JTD AND JRTN PINS

Route a single trace to the ADP1055 from the junction diode

using a trace to JRTN. If single-ended sensing is preferred, tie

the return to AGND using a dedicated trace. Make sure to lay

out the temperature sensor by isolating it and keeping it away

from any direct switch nodes. It is recommended that a 220 nF

to 470 nF capacitor be placed between the base-emitter junctions

of the thermal sensor.

OVP PIN

Route the OVP traces away from any switching nodes to avoid

spuriously tripping the comparator at that pin.

SYNC PIN

It is important to route the trace to the SYNC pin to prevent any

noise from being coupled to the information in the signal. It is

recommended that this trace be kept away from switch nodes

and routed as an internal layer so that the AGND plane acts as a

shield to this trace.

AGND AND DGND

Create an AGND ground plane (preferably in the inner layer)

and make a single-point (star) connection to the power supply

system ground. Connect DGND to AGND with a very short

trace using a star connection. It may be advantageous to have an

entire VDD plane as an additional layer for noise immunity.

J26

HDR1X

+5V

SCL

R55

100Ω

D48

1N4148

R56

100Ω

C63

33pF

C60

33pF

D41

1N4148

D50

1N4148

D43

1N4148

C61

33pF

C62

33pF

SDA

AGND

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