ADP1055ACPZ-R7 datasheet(92/140 Pages) AD

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ADP1055

Data Sheet

Rev. A | Page 92 of 140

Table 154. Register 0xFE29—FFWD_SETTING (Requires Use of the GO Bit in Register 0xFE00)

Bits

Bit Name

R/W

Description

[7:4]

Reserved

R/W

Reserved.

Disable feedforward

during soft start

R/W

If voltage line feedforward is enabled, this bit disables it during the soft start process. This

operation is gated by the filter GO bit (Register 0xFE00).

0 = feedforward enabled during soft start (recommended setting).

1 = feedforward disabled during soft start.

Feedforward enable

R/W

This bit enables the voltage line feedforward loop. This operation is gated by the filter GO bit

(Register 0xFE00]).

0 = feedforward disabled.

1 = feedforward enabled.

LF 8× gain increase

R/W

0 = default.

1 = 8× LF gain.

Global bit for nonlinear

gain

R/W

0 = 1×/1.25×/1.5×/2× gain.

1 = 1×/2×/3×/4× gain.

Table 155. Register 0xFE2A—ISHARE_SETTING

Bits

Bit Name

R/W

Description

[7:4]

Number of bits

dropped by master

R/W

These bits determine how much a master device reduces its output voltage to maintain current

sharing. Each LSB corresponds to 1.6 V/216 = 24 μV (at the VS± pins). This LSB is multiplied or

divided by the setting in the share bus bandwidth register.

[3:0]

Bit difference between

master and slave

R/W

These bits determine how closely a slave tries to match the current of the master device. The

higher the setting, the larger the voltage difference that satisfies the current sharing criteria.

Table 156. Register 0xFE2B—ISHARE_BANDWIDTH

Bits

Bit Name

R/W

Description

[7:5]

Reserved

Reserved.

Bitstream

R/W

1 = the current sense ADC reading is output on the ISHARE pin. This bit stream can be used for

analog current sharing. (recommended setting for standalone power supplies).

0 = the digital share bus signal is output on the ISHARE pin. This signal can be used for digital

current sharing.

Current share select

R/W

1 = CS1 reading used for current share.

0 = CS2 reading used for current share.

[2:0]

Share bus bandwidth

R/W

These bits determine the amount of bandwidth dedicated to the share bus. The value 000 is the

lowest possible bandwidth, and the value 111 is the highest possible bandwidth.

The slave moves up 1 LSB for every share bus transaction (that is, eight data bits plus the start

and stop bits). The master moves down x LSBs per share bus transaction, where x is the share

bus register setting (Register 0xFE2A[7:4]).

0 = divide LSB by 16 (1 LSB = 24 μV/16).

1 = divide LSB by 8.

2 = divide LSB by 4.

3 = divide LSB by 2.

4 = nominal.

5 = multiply LSB by 2.

6 = multiply LSB by 4.

7 = multiply LSB by 8.

8 = multiply LSB by 16.

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