ADP1055ACPZ-R7 datasheet(29/140 Pages) AD

29 / 140 page

Data Sheet

ADP1055

Rev. A | Page 29 of 140

After synchronization, if the master clock suddenly changes to

0 Hz, the ADP1055 continues to operate at the last known master

frequency. However, if the device is power cycled through a soft

start, the master frequency is not retained, and the ADP1055

defaults to the internal frequency set by FREQUENCY_SWITCH

(Register 0x33). If the device is off and the master frequency is

already present on the SYNC pin, the switching frequency is

already set to the master frequency when the ADP1055 turns on.

It is recommended that the synchronization function be

disabled when not in use (Register 0xFE55[6] = 1) because

switching noise may be coupled into the SYNC pin.

The switching frequency can be read back using the PMBus

command READ_FREQUENCY (Register 0x95).

Figure 37. Tracking of SYNC Function

TEMPERATURE SENSING

The ADP1055 has two external temperature sensors. For the

external temperature sensors, PN junction devices such as

transistors are connected back to back; these devices are called

forward diode and reverse diode (see Figure 38).

Figure 38. Temperature Sensor, Forward and Reverse Sensing

The temperature can be read using the following standard PMBus

commands: READ_TEMPERATURE_2 (Register 0x8E) for the

external sensing forward diode, and READ_TEMPERATURE_3

(Register 0x8F) for the external sensing reverse diode.

The ADP1055 measures the temperature readings of the external

forward diode and the external reverse diode in that order. Using

proprietary zero offset circuitry (patent pending), the inputs to

the ADCs are zeroed out before each temperature measurement

to compensate for temperature dependent offset variation, which

affects the measurement result. This allows the forward and

reverse sensing PN diodes to be kept far away from each other

without affecting the reading significantly due to offset errors.

The ADP1055 is factory calibrated at ambient temperature for

minimum error using the BC847A transistor (with nf = 1.00)

placed in the position of forward diode. The nonideality factor

(nf) of the transistor in ΔVBE = nf × VT × ln(I/IS).

Care must be taken to isolate the thermal sensor so that

switching noise is not coupled into the base by the parasitic

capacitances from base to ground and emitter to ground. It is

recommended that a low-pass filter be added by placing a large

capacitor of 220 pF to 470 pF across the base emitter junction to

remove any noise. Adding a reverse diode introduces an

additional error due to the reverse leakage current. The

reference current (IREF), used for the sensing algorithm to 10 μA,

can be programmed by setting Register 0xFE5A[2:0] = 0x04.

The update rate for each subsequent temperature reading

(external forward reading, followed by external reverse reading)

is approximately 200 ms if reverse sensing is enabled, and

approximately 130 ms if reverse sensing is disabled, with 14-bit

resolution (Register 0xFE5A[6:5] = 0x3).

Overtemperature protection (OTP) can be set using

OT_FAULT_LIMIT (Register 0x4F), OT_FAULT_RESPONSE

(Register 0x50), and OT_WARN_LIMIT (Register 0x51). OTP

functions for the forward diode only. The hysteresis for OTP is

the difference between the OT_FAULT_LIMIT and OT_WARN_

LIMIT values. For example, if OT_FAULT_LIMIT is set to disable

all PWM outputs at 125°C and OT_WARN_LIMIT is set to 115°C,

the ADP1055 stops switching at 125°C and begins switching

again only when the temperature falls below 115°C.

GPIO AND PGOOD SIGNALS

Four dedicated pins serve as general-purpose inputs/outputs

(GPIOs). Each pin can be configured as an input or output with

a programmable polarity (set in Register 0xFE40). Do not

change the configuration of the pin from input to output or

from output to input on the fly.

Figure 39. GPIO1 Configured as an Output with Normal Polarity

Figure 40. GPIO1 Configured as an Input with Negated Polarity

When the pin is configured as an input, a programmable action

can be taken (similar to the PMBus voltage faults) using Register

0xFE39 to Register 0xFE3C (GPIOx_FAULT_RESPONSE).

When the GPIOx pin is configured as an output, internal signals

known as PGOOD1 and PGOOD2 can be logically combined

and output on the pin. The logic functions for the GPIO pins

are programmable in Register 0xFE41 and Register 0xFE42.

MASTER CLOCK FREQUENCY (

fSYNC)

SYNCHRONIZATION TIME

DEPENDS ON DPLL BANDWIDTH

SYNCHRONIZATION

TIME DEPENDS ON

DPLL BANDWIDTH

FREQUENCY

NOMINAL

fSW

TIME

INTERNAL SWITCHING FREQUENCY (

fSW)

UNIT

OFF

110%

fSW

90%

fSW

JTD

FORWARD

DIODE

REVERSE

DIODE

JRTN

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