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ADP1055ACPZ-R7 Folha de dados(PDF) 87 Page - Analog Devices

Nome de Peças ADP1055ACPZ-R7
Descrição Electrónicos  Digital Controller for Power Supply Applications with PMBus Interface
PDF  140 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
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ADP1055ACPZ-R7 Folha de dados(HTML) 87 Page - Analog Devices

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Data Sheet
ADP1055
Rev. A | Page 87 of 140
Table 133. Register 0xFE06—LLM_DIGFILT_ZERO_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
Bit Name
R/W
Description
[7:0]
Zero setting
R/W
This register determines the position of the final zero in light load mode. See Figure 85.
Table 134. Register 0xFE07—LLM_DIGFILT_POLE_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
Bit Name
R/W
Description
[7:0]
Pole setting
R/W
This register determines the position of the final pole in light load mode. See Figure 85.
Table 135. Register 0xFE08—LLM_DIGFILT_HF_GAIN_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
Bit Name
R/W
Description
[7:0]
HF gain setting
R/W
This register determines the high frequency gain of the loop response in light load mode. It is
programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 85.
Table 136. Register 0xFE09—SS_DIGFILT_LF_GAIN_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
Bit Name
R/W
Description
[7:0]
LF gain setting
R/W
This register determines the low frequency gain of the loop response in soft start mode. It is
programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 85.
Table 137. Register 0xFE0A—SS_DIGFILT_ZERO_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
Bit Name
R/W
Description
[7:0]
Zero setting
R/W
This register determines the position of the final zero in soft start mode. See Figure 85.
Table 138. Register 0xFE0B—SS_DIGFILT_POLE_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
Bit Name
R/W
Description
[7:0]
Pole setting
R/W
This register determines the position of the final pole in soft start mode. See Figure 85.
Table 139. Register 0xFE0C—SS_DIGFILT_HF_GAIN_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
Bit Name
R/W
Description
[7:0]
HF gain setting
R/W
This register determines the high frequency gain of the loop response in soft start mode. It is
programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 85.
Table 140. Register 0xFE0D, Register 0xFE0F, Register 0xFE11, Register 0xFE13—OUTA_REDGE_SETTING,
OUTB_REDGE_SETTING, OUTC_REDGE_SETTING, OUTD_REDGE_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
Bit Name
R/W
Description
[15:4]
t1, t3, t5, t7
R/W
This register contains the 12-bit t1, t3, t5, t7 time. Each LSB corresponds to 5 ns resolution.
The minimum and maximum possible duty cycle is 0% and 100%, respectively.
3
Modulate enable
R/W
1 = PWM modulation acts on the t1, t3, t5, t7 edge.
0 = no PWM modulation of the t1, t3, t5, t7 edge.
2
t1, t3, t5, t7 sign
R/W
1 = negative sign. Increase of PWM modulation moves t1, t3, t5, t7 right.
0 = positive sign. Increase of PWM modulation moves t1, t3, t5, t7 left.
[1:0]
Reserved
R
Reserved.
Table 141. Register 0xFE0E, Register 0xFE10, Register 0xFE12, Register 0xFE14—OUTA_FEDGE_SETTING,
OUTB_FEDGE_SETTING, OUTC_FEDGE_SETTING, OUTD_FEDGE_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
Bit Name
R/W
Description
[15:4]
t2, t4, t6, t8
R/W
This register contains the 12-bit t2, t4, t6, t8 time. Each LSB corresponds to 5 ns resolution.
The minimum and maximum possible duty cycle is 0% and 100%, respectively.
3
Modulate enable
R/W
1 = PWM modulation acts on the t2, t4, t6, t8 edge.
0 = no PWM modulation of the t2, t4, t6, t8 edge.
2
t2, t4, t6, t8 sign
R/W
1 = negative sign. Increase of PWM modulation moves t2, t4, t6, t8 right.
0 = positive sign. Increase of PWM modulation moves t2, t4, t6, t8 left.
[1:0]
Reserved
R
Reserved.



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