ADP1055ACPZ-R7 datasheet(28/140 Pages) AD

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ADP1055

Data Sheet

Rev. A | Page 28 of 140

ACCURATE OVERVOLTAGE AND UNDERVOLTAGE

PROTECTION

Accurate overvoltage protection is provided by the PMBus

commands VOUT_OV_FAULT_LIMIT (Register 0x40),

VOUT_OV_FAULT_RESPONSE (Register 0x41), and

VOUT_OV_WARN_LIMIT (Register 0x42).

Similarly, accurate undervoltage protection is provided by the

PMBus commands VOUT_UV_WARN_LIMIT (Register 0x43),

VOUT_UV_FAULT_LIMIT (Register 0x44), and VOUT_UV_

FAULT_RESPONSE (Register 0x45).

All readings are obtained from the low frequency Σ-Δ ADC on

the VS+ and VS− pins.

The accurate OVP fault decision is taken after a sampling

interval of 82 μs (7-bit averaged value). For OVP, additional

sampling time up to a maximum of 320 μs can be programmed

in steps of 82 μs using Register 0xFE4D[3:2]. If additional

sampling time is enabled, the OV fault condition must be

present for the number of additional samples programmed

before the VOUT_OV flag is set.

The nominal output voltage at the VS± pins is 1 V, and the OVP

and UVP thresholds are set above and below this level. For UVP,

the output voltage is monitored using the low frequency Σ-Δ ADC;

the nine MSBs of the reading (VS_VALUE, Register 0xFE97[13:5])

are converted into PMBus format and compared with the output

undervoltage fault limit threshold. OVP functions similarly, but

uses the seven MSBs of the reading (Register 0xFE97[13:7]).

FAST OVERVOLTAGE PROTECTION

The ADP1055 has a dedicated OVP pin for redundant overvoltage

protection. This pin performs fast overvoltage protection, where

a comparator compares the fractional output voltage by means of

resistive dividers to the voltage set by a DAC (see Figure 36). The

nominal output voltage at the OVP pin is 1 V. The OVP threshold

is programmable using Register 0xFE2F[7:2]. A debounce time

(from 40 ns to 10 μs) can be added using Register 0xFE2F[1:0]

before the fault response is taken. The fault response is set using

the manufacturer specific command VOUT_OV_FAST_FAULT

(Register 0xFE34).

Figure 36. Fast Overvoltage Protection

EXTERNAL FREQUENCY SYNCHRONIZATION

The ADP1055 has a SYNC pin that is used for frequency

synchronization. The internal digital phase-locked loop (DPLL)

is capable of determining the master frequency on the SYNC pin

(fSYNC) and locking the internal switching frequency to the external

frequency. The lock or capture range is ±10% of the switching

frequency, which is programmed using the FREQUENCY_

SWITCH command (Register 0x33).

The PWM outputs are synchronized to the OUTA pin at the start

of the switching period. For example, consider a duty cycle on

OUTA where the rising (or falling) edge of OUTA is at a time of

x μs after the t = 0 of the switching period. After synchronization,

the time difference between the rising edge of the external master

synchronization frequency (fSYNC) and the rising (or falling) edge

of OUTA is x μs. The other PWM outputs are adjusted accordingly.

In short, frequency synchronization also locks on to the phase.

The DPLL can recognize the external master frequency within

one clock cycle and, after the DPLL has locked on to fSYNC, the

time required to achieve synchronization depends on how far

apart fSYNC and the internal switching frequency (fSW) are. A

typical synchronization time when fSYNC jumps from 90 kHz to

110 kHz with fSW = 100 kHz is approximately 200 μs. The

synchronization time depends on the bandwidth of the DPLL,

which is approximately fSW/25. Therefore, a higher fSW translates

to a higher bandwidth.

Using the INTERLEAVE command (Register 0x37), a phase

shift in steps of 22.5° can be added. Additional functions that

are part of the standard PMBus INTERLEAVE command

include the group ID number and the respective number in the

group, both programmable using Register 0x37.

The ADP1055 supports only a specific number of switching

frequencies. Due to the PWM programming resolution of 5 ns

for programming the minimum and maximum PWM modulation

limit, the switching frequency and the master clock frequency

may not be an exact multiple of each other.

Although the DPLL can detect fSYNC exactly, due to the quantization

of the internal frequency settings, there is a possibility that fSYNC

and fSW may not be the same and may differ by a small amount.

To prevent the frequency from jumping from one value of fSW to

another (which causes the switching period to change) due to

the quantization of fSW, fSW is set to the closest quantized value

to fSYNC rounded down. Due to this effect or due to a non-ideality

(jitter) of the master clock, a dither can be added to the clock

frequency (using Register 0xFE55[1]) of 5 ns or 10 ns. Using

this dither, fSW is equal to fSYNC on average.

For a full-bridge topology, it is recommended that Register

0xFE55[0] = 0 so that half the switching period is an exact

multiple of 5 ns.

6-BIT

THRESHOLD

FAST OVP

0.8V TO 1.6V

STEP SIZE = 12.5mV

DAC

AGND

OVP

ADP1055

VOUT

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