ADP1055ACPZ-R7 datasheet(50/140 Pages) AD

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ADP1055

Data Sheet

Rev. A | Page 50 of 140

PMBUS ADDRESS SELECTION

Control of the ADP1055 is implemented via the I2C interface.

The ADP1055 device is connected to the I2C bus as a slave device

under the control of a master device. The PMBus address of the

ADP1055 is set by connecting an external resistor from the ADD

pin to AGND. Table 11 lists the recommended resistor values

and associated PMBus addresses.

Table 11. PMBus Address Settings

PMBus

Addr 1

PMBus

Addr 2

PMBus

Addr 3

PMBus

Addr 4

1% Resistor (Ω)

(E96 series)

0x40

0x50

0x60

0x70

210 (or connect

to AGND)

0x41

0x51

0x61

0x71

750

0x42

0x52

0x62

0x72

1330

0x43

0x53

0x63

0x73

2050

0x44

0x54

0x64

0x74

2670

0x45

0x55

0x65

0x75

3570

0x46

0x56

0x66

0x76

4420

0x47

0x57

0x67

0x77

5360

0x48

0x58

0x68

0x78

6340

0x49

0x59

0x69

0x79

7320

0x4A

0x5A

0x6A

0x7A

8450

0x4B

0x5B

0x6B

0x7B

9530

0x4C

0x5C

0x6C

0x7C

10,700

0x4D

0x5D

0x6D

0x7D

12,100

0x4E

0x5E

0x6E

0x7E

13,700

0x4F

0x5F

0x6F

0x7F

15,000 (or connect

to VDD)

Using a resistor enables the selection of 16 different base addresses

from 0x40 to 0x4F. Additional addresses can be selected using the

SLV_ADDR_SELECT command (Register 0xD0). For example,

a device can be programmed to have an address of 0x65 by

connecting a 3.57 kΩ resistor at the ADD pin and programming

time that the power is cycled to the ADP1055, the device responds

to an address of 0x65. Other addresses can be selected.

If an incorrect resistor value is used and the resulting I2C

address is close to a threshold between two addresses, the

STATUS_UNKNOWN flag is set (Register 0xFE94[3]). It is

recommended that 1% tolerance resistors be used on the ADD

pin. However, 5% resistors can be selected, but the use of some

of the addresses will not be allowed due to the overlap of

address ranges.

In addition to its programmed address, the ADP1055 responds

to the standard PMBus broadcast address (general call) of 0x00.

FAST MODE

Fast mode (400 kHz) uses essentially the same mechanics as

the standard mode of operation; the electrical specifications

and timing are most affected. The PMBus slave is capable of

communicating with a master device operating in standard

mode (100 kHz) or fast mode.

10-BIT ADDRESSING

The PMBus slave device does not support 10-bit addressing as

defined in the I2C specification.

PACKET ERROR CHECKING

The PMBus controller implements packet error checking (PEC)

to improve reliability and communication robustness. Packet

error checking is implemented by appending a PEC byte at the

end of the message transfer. The PEC byte is calculated using a

CRC-8 algorithm on all ADDR, CMD, and DATA bytes from

the start to stop bits (excluding the ACK, NACK, start, restart,

and stop bits). The PEC byte is appended to the end of the

message by the device that supplied the last data byte. The

receiver of the PEC byte is responsible for calculating its

internal PEC code and comparing it to the received PEC byte.

The ADP1055 can communicate with master PMBus devices that

support PEC, as well as with master devices that do not support

PEC. If a PEC byte is available, the PMBus device checks the

PEC byte and issues an acknowledge (ACK) if the PEC byte is

correct. If the PEC byte comparison fails, the PMBus device

issues a no acknowledge (NACK) in response to the PEC byte

and does not process the command sent from the master.

The PMBus device uses built-in hardware to calculate the PEC

code using the CRC-8 polynomial, C(x) = x8 + x2 + x1 + 1. The

PEC code is calculated one byte at a time, in the order that it is

received. In a read transaction, the PMBus device appends the

PEC byte following the last data byte. In a write transaction, the

PMBus device compares the received PEC byte to the internally

calculated PEC code.

ELECTRICAL SPECIFICATIONS

All logic complies with the Electrical Specification outlined in

the PMBus Power System Management Protocol Specification

Part 1, Revision 1.2, dated September 6, 2010.

FAULT CONDITIONS

The PMBus protocol provides a comprehensive set of fault

conditions that must be monitored and reported. These fault

conditions can be grouped into two major categories: commu-

nication faults and monitoring faults.

Communication faults are error conditions associated with the

data transfer mechanism of the PMBus protocol (see the following

sections for more information).

Monitoring faults are error conditions associated with the

operation of the PMBus device, such as output overvoltage

protection, and are specific to each PMBus device. For more

information about the monitoring fault conditions, see the Fault

Responses and State Machine Mechanics section.

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