ADIN1300BCPZ-R7 datasheet(20/79 Pages) AD

20 / 79 page

ADIN1300

Data Sheet

Rev. 0 | Page 20 of 79

MDI INTERFACE

The MDI connects the ADIN1300 to the Ethernet network via a

transformer, as shown in Figure 24. In 1000BASE-T mode,

transmit and receive occur simultaneously on each of the MDI_

x_x pairs. In 10BASE-Te and 100BASE-TX modes, MDI_0_x are

used to transmit when operating in MDI configuration and to

receive when operating in MDIX configuration. The opposite is

true of MDI_1_x in 10BASE-Te mode and 100BASE-TX mode.

For example, MDI_1_x are used to receive when operating in

MDI configuration and to transmit when operating in MDIX

configuration. If auto MDIX is enabled, the ADIN1300

automatically determines if the MDI or MDIX configuration

must be used. Otherwise, it is forced to the chosen MDI or

MDIX configuration. In 10BASE-Te mode and 100BASE-TX

mode, MDI_2_x and MDI_3_x are unused.

ADIN1300

RJ45

MDI_0_P

MDI_0_N

MDI_1_P

MDI_1_N

MDI_2_P

MDI_2_N

MDI_3_P

MDI_3_N

Figure 24. Media Dependent Interface

RESET OPERATION

The ADIN1300 supports a number of resets that include

power-on reset, hardware reset, and multiple software reset

types. All of these put the ADIN1300, including the PHY core,

in a known state. Whenever the PHY core is reset, the MAC

interface output pins (output pins with respect to the ADIN1300)

are driven to a known idle state. All outputs except RXC/RX_CLK

are driven low and RXC/RX_CLK is driven high.

Power-On Reset

The ADIN1300 includes power monitoring circuitry to monitor

all of the supplies. At power-up, the ADIN1300 is held in

hardware reset until each of the supplies has crossed its minimum

rising threshold value.

Brown-out protection is provided by monitoring the supplies to

detect if one or more of the supplies drops below a minimum

falling threshold value and holding the device in hardware reset

until the power is valid again.

Table 17. Brown-Out Protection Threshold Values

Supply

Minimum Falling Threshold Value (V)

AVDD_3P3

2.35

VDDIO

1.35

DVDD_0P9

0.7

Hardware Reset

A hardware reset is initiated by the POR circuitry or by asserting

the RESET_N pin low. Bring the pin low for a minimum of

10 μs. Deglitch circuitry is included on this pin to reject pulses

shorter than ~1 μs.

When the RESET_N pin is deasserted, the crystal oscillator

circuit is enabled and the clock is given time to stabilize. The

state of the hardware configuration pins is read and latched, the

digital and analog circuits are initialized, and the PHY core clock

multiplier unit (CMU) is reset. After 5 ms from the deassertion

of RESET_N, the management interface registers are accessible

and the device can be programmed. This time is significantly

shorter if a single-ended clock rather than a crystal is used and

the management interface registers are accessible 3 ms after the

deassertion of RESET_N. If the ADIN1300 is configured to

enter software power-down after a reset (see Table 23), the

ADIN1300 enters software power-down mode and an interrupt

is generated to indicate that a hardware reset occurred.

The following events occur after a hardware reset:



The crystal oscillator circuit is enabled and time is allowed

for the clock to stabilize.



The hardware configuration pins are read and the values

latched. These set the default values of the pin-dependent

registers in the subsystem and PHY core registers.



The MAC interface block is reset.



The PHY core is reset.



The PHY core CMU is reset.



An interrupt to indicate that a hardware reset occurred is

generated depending on the pin configuration (if the

ADIN1300 was configured to enter software power-down

mode after reset).

Software Reset

The ADIN1300 supports the following different software resets

that reset specific circuit blocks under software control:



Subsystem software reset with pin configuration



Subsystem software reset



PHY core software reset

Subsystem Software Reset with Pin Configuration

The ADIN1300 supports a software reset capability that behaves

in a similar way to a hardware reset (see Table 18) (see the

Subsystem Register Summary section). A subsystem reset with a

pin configuration can be initiated by setting the GE_SFT_

RST_CFG_EN bit (Address 0xFF0D) to 1 before setting

GE_SFT_RST bit (Address 0xFF0C) to 1. This subsystem

software reset follows the same reset sequence as the POR and

hardware reset, except the crystal oscillator is not disabled and

the clock stabilization step is skipped. The state of the hardware

configuration pins is read and latched. These configuration pins

set the default values of the pin dependent registers in the

subsystem and PHY core registers. The MAC interface block

and PHY core are reset. If a 125 MHz clock is selected as the

PHY output clock, the GP_CLK pin, the PHY core CMU is not

reset. Otherwise, the CMU is reset. The main difference

between this type of reset and a hardware reset is that the

crystal oscillator is not disabled.

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