ADIN1300BCPZ-R7 datasheet(17/79 Pages) AD

17 / 79 page

Data Sheet

ADIN1300

Rev. 0 | Page 17 of 79

MAC INTERFACE

The ADIN1300 provides the option of RGMII, MII, or RMII

MAC interface. The MAC interface is selected using hardware

configuration pins (see Table 25) or via software.

RGMII Interface Mode

MAC

RXC

RXD_0 TO RXD_3

RX_CTL

TXC

TXD_0 TO TXD_3

TX_CTL

PHY

Figure 20. RGMII MAC-PHY Interface Signals

The RGMII interface is capable of supporting data rates of

1 Gbps, 100 Mbps, and 10 Mbps. For the receive interface, the

ADIN1300 generates a 125 MHz, 25 MHz, or 2.5 MHz RXC

signal to synchronize the RXD_x pin receive data in 1000BASE-T,

100BASE-TX, or 10BASE-Te modes, respectively. The RX_CTL

is a combination of the RX_DV and RX_ER signals (as described

in the MII Interface Mode section) using both edges of the RXC

signal. The ADIN1300 transmits the RX_DV signal on the

positive edge of RXC and a combination (XOR function) of

RX_DV and RX_ER on the negative edge of RXC.

For the transmit interface, when operating in 1000BASE-T mode,

the MAC drives TXC with a 125 MHz clock signal. The MAC

transmits the TXD_x pin data, Bits[3:0] on the positive edge of

TXC and TXD_x pin data, Bits[7:4] on the negative edge of

TXC. In 100BASE-TX and 10BASE-Te modes, TXC is at 25 MHz

and 2.5 MHz, respectively, and the MAC transmits the TXD_x pin

data, Bits[3:0] on both edges of TXC. TX_CTL is a combination

of the TX_EN and TX_ER signals using both edges of TXC.

TX_EN is transmitted on the positive edge of TXC, and TX_EN

XOR TX_ER is transmitted on the negative edge of TXC. Due

to the fact that data is transmitted on both edges of the clock, an

accurate delay requirement of 2 ns is required on both clock

edges (see Figure 21) to ensure that the delayed clock is at the

center of the data window, ensuring accurate data capture. It is

possible to enable this 2 ns delay on RXC only or on both RXC

and TXC using hardware pin configuration settings (see Table 25).

These delays can also be configured in software. In Figure 21,

the 8 ns period refers to 1000BASE-T operation, which is 40 ns

or 400 ns in the case of 100BASE-TX and 10BASE-Te, respectively.

The 2 ns delay is valid for 10BASE-Te, 100BASE-TX, and

1000BASE-T.

D0L

TXD

(FROM MAC)

TXC

(FROM MAC)

TXC

(INTERNAL DELAY)

D1L

D0H

8ns

2ns

Figure 21. DLL Waveform

MII Interface Mode

MAC

RX_CLK

RXD_0 TO RXD_3

RX_DV

TX_CLK

TXD_0 TO TXD_3

TX_EN

PHY

RX_ER

COL

CRS

TX_ER

Figure 22. MII MAC to PHY Interface Signals

The MII interface is capable of supporting data rates of 100 Mbps

and 10 Mbps. For the receive interface, the ADIN1300 generates

a 25 MHz or 2.5 MHz RX_CLK signal to synchronize the

RXD_x pin receive data in 100BASE-TX or 10BASE-Te modes,

respectively. RX_DV indicates to the MAC that there is valid

data present on the RXD_x receive pin. RX_ER is driven high

by the ADIN1300 if an error is detected in the frame that was

received from the MDI interface and is being transmitted to the

MAC, or during a false carrier event (in 100BASE-TX mode).

The CRS pin indicates the presence of a carrier to the MAC,

while the COL pin is asserted in a collision condition.

For the transmit interface, the PHY generates a 25 MHz or

2.5 MHz reference clock on TX_CLK. The MAC transmits data

on the TXD_x transmit pin that is synchronized with TX_CLK.

The MAC asserts the TX_EN pin to indicate to the ADIN1300

that transmission data is available on the TXD_x transmit data

lines. Because the TX_ER pin is not used in 10BASE-Te mode,

and it is only used in 100BASE-TX mode for forward error

propagation and for EEE low power idle (LPI) request, TX_ER

is only supported when EEE is enabled via the hardware

configuration pins (see Table 14).

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