ADIN1300BCPZ-R7 datasheet(51/79 Pages) AD

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Data Sheet

ADIN1300

Rev. 0 | Page 51 of 79

PHY Control 3 Register

Address: 0x0017, Reset: 0x3048, Name: PHY_CTRL_3

This register provides access to PHY control register bits for link enable and autonegotiation controls.

Table 50. Bit Descriptions for PHY_CTRL_3

Bits

Bit Name

Description

Reset

Access

[15:14]

RESERVED

Reserved.

0x0

LINK_EN

Setting this bit enables linking. If linking is disabled, the PHY enters the standby state

and does not attempt to bring up links. The standby state can be used to run

diagnostics, including cable diagnostics.

0x1

R/W

1: enable linking.

0: disable linking.

[12:10]

NUM_SPEED_RETRY

If downspeed is enabled, this register bit specifies the number of retries the PHY must

attempt to bring up a link at the advertised speed before advertising a lower speed. By

default, the PHY attempts to bring up a link 5 times (4 retries) before downspeeding.

0x4

R/W

[9:0]

RESERVED

Reserved.

0x48

R/W

Interrupt Mask Register

Address: 0x0018, Reset: 0x0000, Name: IRQ_MASK

The interrupt mask register allows interrupts to be masked or unmasked.

Table 51. Bit Descriptions for IRQ_MASK

Bits

Bit Name

Description

Reset

Access

[15:11]

RESERVED

Reserved.

0x0

R/W

CBL_DIAG_IRQ_EN

Cable Diagnostics Interrupt Enable Bit.

0x0

R/W

1: enable cable diagnostics interrupt.

0: disable cable diagnostics interrupt.

MDIO_SYNC_IRQ_EN

MDIO Synchronization Lost Interrupt Enable Bit.

0x0

R/W

1: enable MDIO synchronization lost interrupt.

0: disable MDIO synchronization lost interrupt.

AN_STAT_CHNG_IRQ_EN

Autonegotiation Status Changed Interrupt Enable Bit.

0x0

R/W

1: enable autonegotiation status changed interrupt.

0: disable autonegotiation status changed interrupt.

RESERVED

Reserved.

0x0

R/W

PAGE_RX_IRQ_EN

Autonegotiation Page Received Interrupt Enable Bit.

0x0

R/W

1: enable autonegotiation page received interrupt.

0: disable autonegotiation page received interrupt.

IDLE_ERR_CNT_IRQ_EN

Idle Error Counter Saturated Interrupt Enable Bit.

0x0

R/W

1: enable idle error counter saturated interrupt.

0: disable idle error counter saturated interrupt.

FIFO_OU_IRQ_EN

MAC Interface FIFO Overflow/Underflow Interrupt Enable Bit.

0x0

R/W

1: enable MAC interface FIFO overflow/underflow interrupt.

0: disable MAC interface FIFO overflow/underflow interrupt.

RX_STAT_CHNG_IRQ_EN

Receive Status Changed Interrupt Enable Bit.

0x0

R/W

1: enable receive status changed interrupt.

0: disable receive status changed interrupt.

LNK_STAT_CHNG_IRQ_EN

Link Status Changed Interrupt Enable Bit.

0x0

R/W

1: enable link status changed interrupt.

0: disable link status changed interrupt.

SPEED_CHNG_IRQ_EN

Speed Changed Interrupt Enable Bit.

0x0

R/W

1: enable speed changed interrupt.

0: disable speed changed interrupt.

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