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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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ADIN1300BCPZ-R7 Folha de dados(PDF) 44 Page - Analog Devices |
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ADIN1300BCPZ-R7 Folha de dados(HTML) 44 Page - Analog Devices |
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44 / 79 page  ADIN1300 Data Sheet Rev. 0 | Page 44 of 79 Bits Bit Name Description Reset Access 8 FD_100_ADV The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit is to advertise 100BASE-TX full duplex. Note that the default value of this register bit is configurable via the hardware configuration pins, which allows the default operation of the PHY to be configured in unmanaged applications. 0x1 R/W 7 HD_100_ADV The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit is to advertise 100BASE-TX half duplex. Note that the default value of this register bit is configurable via the hardware configuration pins, which allows the default operation of the PHY to be configured in unmanaged applications. 0x1 R/W 6 FD_10_ADV The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit is to advertise 10BASE-T full duplex. Note that the default value of this register bit is configurable via the hardware configuration pins, which allows the default operation of the PHY to be configured in unmanaged applications. 0x1 R/W 5 HD_10_ADV The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit is to advertise 10BASE-T half duplex. Note that the default value of this register bit is configurable via the hardware configuration pins, which allows the default operation of the PHY to be configured in unmanaged applications. 0x1 R/W [4:0] SELECTOR_ADV Selector field is a 5-bit wide field, encoding 32 possible messages. This field always reads as 1'b1, indicating that the PHY only supports IEEE Standard 802.3. 0x1 R/W Autonegotiation Link Partner Base Page Ability Register Address: 0x0005, Reset: 0x0000, Name: LP_ABILITY This address corresponds to the link partner ability register specified in Clause 28.2.4.1.4 of IEEE Standard 802.3. Table 36. Bit Descriptions for LP_ABILITY Bits Bit Name Description Reset Access 15 LP_NEXT_PAGE Link Partner Next Page Bit. Next page exchange occurs after the base link code words have been exchanged. Next page exchange consists of using the normal autonegotiation arbitration process to send next page messages. Next page transmission ends when both ends of a link segment set their next page bits to Logic 0, indicating that neither has anything additional to transmit. 0x0 R 14 LP_ACK This bit is used by the internal handshaking in autonegotiation and must be ignored. 0x0 R 1: link partner has successfully received its link code word. 0: link partner has not received its link code word. 13 LP_REM_FLT The link partner remote fault bit provides a standard transport mechanism for the transmission of simple fault information. 0x0 R 12 LP_EXT_NEXT_PAGE_ABLE The link partner extended next page bit indicates that the link partner supports transmission of extended next page. The use of extended next page is orthogonal to the negotiated data rate, medium, or link technology. 0x0 R 11 LP_APAUSE_ABLE The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit indicates that the link partner advertises asymmetric pause operation for full duplex links. 0x0 R 10 LP_PAUSE_ABLE The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit indicates that the link partner advertises pause operation for full duplex links. 0x0 R 9 LP_T_4_ABLE The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit indicates that the link partner advertises 100BASE-T4. 0x0 R 8 LP_FD_100_ABLE The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit indicates that the link partner advertises 100BASE-TX full duplex. 0x0 R 7 LP_HD_100_ABLE The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit indicates that the link partner advertises 100BASE-TX half duplex. 0x0 R |
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