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ADIN1300BCPZ-R7 Folha de dados(PDF) 43 Page - Analog Devices

Nome de Peças ADIN1300BCPZ-R7
Descrição Electrónicos  Robust, Industrial, Low Latency and Low Power 10 Mbps
PDF  79 Pages
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ADIN1300BCPZ-R7 Folha de dados(HTML) 43 Page - Analog Devices

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Data Sheet
ADIN1300
Rev. 0 | Page 43 of 79
Bits
Bit Name
Description
Reset
Access
1
JABBER_DET_LAT
Jabber Detect Bit. When this bit goes high, it latches high until it is unlatched by reading.
0x0
R
1: jabber condition detected.
0: no jabber condition detected.
0
EXT_CAPABLE
The extended capability bit always reads as 1'b1 because the PHY provides an
extended set of capabilities.
0x1
R
PHY Identifier 1 Register
Address: 0x0002, Reset: 0x0283, Name: PHY_ID_1
This address corresponds to the MII status register specified in Clause 22.2.4.3.1 of IEEE Standard 802.3 and allows 16 bits of the
organizationally unique identifier (OUI) to be observed.
Table 33. Bit Descriptions for PHY_ID_1
Bits
Bit Name
Description
Reset
Access
[15:0]
PHY_ID_1
Organizationally Unique Identifier Bits[3:18].
0x283
R
PHY Identifier 2 Register
Address: 0x0003, Reset: 0xBC30, Name: PHY_ID_2
This address corresponds to the MII status register specified in Clause 22.2.4.3.1 of IEEE Standard 802.3 and allows 6 bits of the OUI
along with the model number and revision number to be observed.
Table 34. Bit Descriptions for PHY_ID_2
Bits
Bit Name
Description
Reset
Access
[15:10]
PHY_ID_2_OUI
Organizationally Unique Identifier Bits[19:24].
0x2F
R
[9:4]
MODEL_NUM
Manufacturer Model Number.
0x3
R
[3:0]
REV_NUM
Manufacturer Revision Number.
0x0
R
Autonegotiation Advertisement Register
Address: 0x0004, Reset: 0x01E1, Name: AUTONEG_ADV
This address corresponds to the autonegotiation advertisement register specified in Clause 28.2.4.1.3 of IEEE Standard 802.3. Note that
the default reset value of this register is dependent on the hardware configuration pins settings.
Table 35. Bit Descriptions for AUTONEG_ADV
Bits
Bit Name
Description
Reset
Access
15
NEXT_PAGE_ADV
Next page exchange occurs after the base link codewords have been exchanged. Next
page exchange consists of using the normal autonegotiation arbitration process to send
next page messages. Next page transmission ends when both ends of a link segment set
their next page bits to Logic 0, indicating that neither has anything additional to transmit.
0x0
R/W
14
RESERVED
Reserved.
0x0
R
13
REM_FLT_ADV
The remote fault bit provides a standard transport mechanism for the transmission of
simple fault information.
0x0
R/W
12
EXT_NEXT_PAGE_ADV
The extended next page bit indicates that the local device supports transmission of
extended next pages. The use of extended next page is orthogonal to the negotiated
data rate, medium, or link technology.
0x0
R/W
11
APAUSE_ADV
The technology ability field is a 7-bit wide field (Bits[11:5] within this register)
containing information indicating supported technologies specific to the selector field
value. This bit is to advertise asymmetric pause operation for full duplex links.
0x0
R/W
10
PAUSE_ADV
The technology ability field is a 7-bit wide field (Bits[11:5] within this register)
containing information indicating supported technologies specific to the selector field
value. This bit is to advertise pause operation for full duplex links.
0x0
R/W
9
T_4_ADV
The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing
information indicating supported technologies specific to the selector field value. This
bit is to advertise 100BASE-T4 and always reads as 1'b0 because this technology is not
supported.
0x0
R



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