ADIN1300BCPZ-R7 datasheet(41/79 Pages) AD

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Data Sheet

ADIN1300

Rev. 0 | Page 41 of 79

Address

Name

Description

Reset

Access

0xBA1F

CDIAG_DTLD_RSLTS_2

Cable Diagnostics Results 2 Register.

0x0000

0xBA20

CDIAG_DTLD_RSLTS_3

Cable Diagnostics Results 3 Register.

0x0000

0xBA21

CDIAG_FLT_DIST_0

Cable Diagnostics Fault Distance Pair 0 Register.

0x00FF

0xBA22

CDIAG_FLT_DIST_1

Cable Diagnostics Fault Distance Pair 1 Register.

0x00FF

0xBA23

CDIAG_FLT_DIST_2

Cable Diagnostics Fault Distance Pair 2 Register.

0x00FF

0xBA24

CDIAG_FLT_DIST_3

Cable Diagnostics Fault Distance Pair 3 Register.

0x00FF

0xBA25

CDIAG_CBL_LEN_EST

Cable Diagnostics Cable Length Estimate Register.

0x00FF

0xBC00

LED_PUL_STR_DUR

LED Pulse Stretching Duration Register.

0x0011

R/W

PHY CORE REGISTER DETAILS

MII Control Register

Address: 0x0000, Reset: 0x1040, Name: MII_CONTROL

This address corresponds to the MII control register specified in Clause 22.2.4.1 of Standard 802.3. Note that the default reset value of this

Table 31. Bit Descriptions for MII_CONTROL

Bits

Bit Name

Description

Reset

Access

SFT_RST

Software Reset Bit. Note that this bit is self clearing. When the reset operation is complete,

this bit returns to 1'b0.

0x0

R/W

1: PHY reset.

0: normal operation.

LOOPBACK

Enable/Disable Loopback Mode.

0x0

R/W

1: enable loopback mode.

0: disable loopback mode.

SPEED_SEL_LSB

The speed selection MSB and LSB register bits are used to configure the link speed. Note that

the default value of this register bit is configurable via the hardware configuration pins. This

allows the default operation of the PHY to be configured in unmanaged applications.

0x0

R/W

11: reserved.

10: 1 Gbps.

01: 100 Mbps.

00: 10 Mbps.

AUTONEG_EN

The autonegotiation enable bit is used to enable/disable autonegotiation. Note that the

default value of this register bit is configurable via the hardware configuration pins. This

allows the default operation of the PHY to be configured in unmanaged applications.

0x1

R/W

1: enable autonegotiation process.

0: disable autonegotiation process.

SFT_PD

Software Power-Down Bit. Note that the default value of this register bit is configurable via

the hardware configuration pins. The PHY can be held in reset until initialized by the software.

0x0

R/W

1: software power-down.

0: normal operation.

ISOLATE

Isolate Bit.

0x0

R/W

1: electrically isolate PHY from MAC interface by setting MAC interface pins to tristate (even if

active).

0: normal operation.

RESTART_ANEG

Restart Autonegotiation Bit. Note that this bit is self clearing. When the autonegotiation

process is restarted, this bit returns to 1'b0.

0x0

R/W

1: restart the autonegotiation process.

0: normal operation.

DPLX_MODE

Duplex Mode Bit.

0x0

R/W

1: full duplex.

0: half duplex.

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