ADIN1300BCPZ-R7 datasheet(59/79 Pages) AD

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Data Sheet

ADIN1300

Rev. 0 | Page 59 of 79

Bits

Bit Name

Description

Reset

Access

FLD_SLCR_OUT_STUCK_B_1000_EN

Enhanced link detection PMA slicer output stuck at detection enable for

1000BASE-T.

0x1

R/W

FLD_SLCR_IN_ZDET_B_100_EN

Enhanced link detection PMA slicer input zero detection enable for

100BASE-TX.

0x1

R/W

FLD_SLCR_IN_ZDET_B_1000_EN

Enhanced link detection PMA slicer input zero detection enable for

1000BASE-T.

0x1

R/W

FLD_SLCR_IN_INVLD_B_100_EN

Enhanced link detection PMA slicer input invalid level detection enable

for 100BASE-TX. Enabled when set high.

0x0

R/W

FLD_SLCR_IN_INVLD_B_1000_EN

Enhanced link detection PMA slicer input invalid level detection enable

for 1000BASE-T. Enabled when set high.

0x1

R/W

Enhanced Link Detection Latched Status Register

Address: 0x8E38, Reset: 0x0000, Name: FLD_STAT_LAT

This register is the latched status for the enhanced link detection function. This bit is latched until the start of the next link-up, when it is

cleared.

Table 67. Bit Descriptions for FLD_STAT_LAT

Bits

Bit Name

Description

Reset

Access

[15:14]

RESERVED

Reserved.

0x0

FAST_LINK_DOWN_LAT

Main Enhanced Link Detection Latched Indication.

0x0

[12:0]

RESERVED

Reserved.

0x0

Receive MII Clock Stop Enable Register

Address: 0x9400, Reset: 0x0400, Name: RX_MII_CLK_STOP_EN

This register contains the clock stop enable bit specified in Clause 45.2.3.1.4 of IEEE Standard 802.3, which, in the IEEE standard, is at

MMD Register Address 3.0, Bit 10.

Table 68. Bit Descriptions for RX_MII_CLK_STOP_EN

Bits

Bit Name

Description

Reset

Access

[15:11]

RESERVED

Reserved.

0x0

RX_MII_CLK_STOP_EN

If this bit is set, the PHY may stop the receive MII clock while it is signaling low power

enable (LPI). Otherwise, it keeps the clock active.

0x1

R/W

1: the PHY may stop the clock during LPI.

0: clock not stoppable.

[9:0]

RESERVED

Reserved.

0x0

PCS Status 1 Register

Address: 0x9401, Reset: 0x0040, Name: PCS_STATUS_1

The bits contained in this register correspond to the bits in the PCS Status 1 register specified in Clause 45.2.3.2 of IEEE Standard 802.3,

which, in the IEEE standard, is at MMD Register Address 3.1, Bits[11:8] and Bit 6.

Table 69. Bit Descriptions for PCS_STATUS_1

Bits

Bit Name

Description

Reset

Access

[15:12]

RESERVED

Reserved.

0x0

TX_LPI_RCVD

The transmit LPI received bit is a latched version of TX_LPI. When this bit goes

high, it latches high until it is unlatched by reading.

0x0

1: transmit PCS has received LPI.

0: LPI not received.

RX_LPI_RCVD

The receive LPI received bit is a latched version of RX_LPI. When this bit goes high,

it latches high until it is unlatched by reading.

0x0

1: receive PCS has received LPI.

0: LPI not received.

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