ADIN1300BCPZ-R7 datasheet(48/79 Pages) AD

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ADIN1300

Data Sheet

Rev. 0 | Page 48 of 79

Extended Status Register

Address: 0x000F, Reset: 0x3000, Name: EXT_STATUS

This address corresponds to the extended status register specified in Clause 22.2.4.4 of IEEE Standard 802.3.

Table 42. Bit Descriptions for EXT_STATUS

Bits

Bit Name

Description

Reset

Access

FD_1000_X_SPRT

This bit is always zero because the PHY does not support full duplex 1000BASE-X.

0x0

HD_1000_X_SPRT

This bit is always zero because the PHY does not support half duplex 1000BASE-X.

0x0

FD_1000_SPRT

This bit is always one because the PHY supports full duplex 1000BASE-T.

0x1

HD_1000_SPRT

This bit is always one because the PHY supports half duplex 1000BASE-T.

0x1

[11:0]

RESERVED

Reserved.

0x0

Extended Register Pointer Register

Address: 0x0010, Reset: 0x0000, Name: EXT_REG_PTR

The extended register pointer and extended register data registers provide a mechanism to access the indirect access address map via

directly accessible registers for cases where the station management does not support Clause 45.

Table 43. Bit Descriptions for EXT_REG_PTR

Bits

Bit Name

Description

Reset

Access

[15:0]

EXT_REG_PTR

The extended register pointer and extended register data registers provide an indirect mechanism

to access EMI registers using normal Clause 22 access for cases where the station management

does not support Clause 45. Write the 16-bit register address into the EXT_REG_PTR register.

The EMI register can be read or written by reading or writing the EXT_REG_DATA register. An

EMI register can be directly accessed using Clause 45 access.

0x0

R/W

Extended Register Data Register

Address: 0x0011, Reset: 0x0000, Name: EXT_REG_DATA

The extended register pointer and extended register data registers provide a mechanism to access the indirect access address map via

directly accessible registers for cases where the station management does not support Clause 45.

Table 44. Bit Descriptions for EXT_REG_DATA

Bits

Bit Name

Description

Reset

Access

[15:0]

EXT_REG_DATA

The extended register pointer and extended register data registers provide an indirect

mechanism to access EMI registers using normal Clause 22 access for cases where the station

management does not support Clause 45. See Table 43 for further details.

0x0

R/W

PHY Control 1 Register

Address: 0x0012, Reset: 0x0002, Name: PHY_CTRL_1

This register provides access to various PHY control register bits, in particular for diagnostic clocking control and MDI crossover.

Table 45. Bit Descriptions for PHY_CTRL_1

Bits

Bit Name

Description

Reset

Access

[15:11]

RESERVED

Reserved.

0x0

AUTO_MDI_EN

The automatic MDI/MDIX resolution enable register bit allows the automatic cable crossover

feature of the PHY to be controlled. Note that the default value of this register bit is configurable

via a hardware configuration pin, which allows the default operation of the PHY to be

configured in unmanaged applications.

0x0

R/W

1: enable auto MDI/MDIX. Prefer MDI if MAN_MDIX is 1'b0 and prefer MDIX if MAN_MDIX is 1'b1.

0: disable auto MDI/MDIX.

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