ADIN1300BCPZ-R7 datasheet(9/79 Pages) AD

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Data Sheet

ADIN1300

Rev. 0 | Page 9 of 79

Parameter

Description

Min

Typ

Max

Unit

Duty_G

Duty cycle for Gigabit

Duty_T

Duty cycle for 10/100 Mbps

tR/tF

Rise/fall time (20% to 80%)

0.75

1 When operating without RGMII internal delay, the printed circuit board (PCB) design requires clocks to be routed such that an additional trace delay of greater than

1.5 ns and less than 2.0 ns is added to the associated clock signal. For 10/100 Mbps, the max value is unspecified.

2 Hardware and software programmable internal delay may be enabled or disabled.

3 For 10 Mbps and 100 Mbps, tCYC scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

TXC

(AT TRANSMITTER)

TXD_0 TO TXD_3

TX_CTL

TXC

(AT RECEIVER)

TXD_x,

Bits[3:0]

TXD_x,

Bits[7:4]

TXEN

TXERR

TXC WITH INTERNAL DELAY ADDED

Figure 7. RGMII Transmit Timing

RXC

(AT TRANSMITTER)

RXD_0 TO RXD_3

RX_CTL

RXC

(AT RECEIVER)

RXD_x,

Bits[3:0]

RXD_x,

Bits[7:4]

RXEN

RXERR

RXC WITH INTERNAL DELAY ADDED

Figure 8. RGMII Receive Timing

RMII Transmit/Receive

Table 10. RMII Timing

Parameter

Description

Min

Typ

Max

Unit

REF_CLK Frequency

Frequency of the REF_CLK

MHz

REF_CLK Duty Cycle

Duty Cycle of the REF_CLK

TXD_0, TXD_1, TX_EN, RXD_0, RXD_1, CRS_DV,

RX_ER data setup to REF_CLK rising edge

TXD_0, TXD_1, TX_EN, RXD_0, RXD_1, CRS_DV,

RX_ER data hold from REF_CLK rising edge

Output rise/fall time

REF_CLK

TXD_0 AND TXD_1

TX_EN

RXD_0 AND RXD_1

CRS_DV

RX_ER

Figure 9. RMII Timing

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