ADIN1300BCPZ-R7 datasheet(50/79 Pages) AD

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ADIN1300

Data Sheet

Rev. 0 | Page 50 of 79

PHY Control Status 2 Register

Address: 0x0015, Reset: 0x0000, Name: PHY_CTRL_STATUS_2

This register provides access to various PHY control and status registers, in particular autonegotiation controls and energy detect power-

down control and status bits.

Table 48. Bit Descriptions for PHY_CTRL_STATUS_2

Bits

Bit Name

Description

Reset

Access

[15:4]

RESERVED

Reserved.

0x0

NRG_PD_EN

Setting this bit enables energy detect power-down. If there is no signal energy detected for

a number of seconds, the PHY enters energy detect power-down mode. Note that the

default value of this register bit is configurable via the hardware configuration pins. This

allows the default operation of the PHY to be configured in unmanaged applications.

0x0

R/W

1: enable energy detect power-down mode.

0: disable energy detect power-down mode.

NRG_PD_TX_EN

When this bit is set, the PHY periodically wakes up when in energy detect power-down and

transmits a number of pulses. This is to avoid a lock up situation where the PHYs on both

ends of the line are in energy detect power-down mode. Note that the default value of this

operation of the PHY to be configured in unmanaged applications.

0x0

R/W

1: enable periodic transmission of the pulse while in energy detect power-down mode.

0: disable periodic transmission of the pulse while in energy detect power-down mode.

PHY_IN_NRG_PD

This status bit indicates that the PHY is in energy detect power-down mode.

0x0

1: PHY is in energy detect power-down mode.

0: PHY is not in energy detect power-down mode.

RESERVED

Reserved.

0x0

R/W

PHY Control 2 Register

Address: 0x0016, Reset: 0x0308, Name: PHY_CTRL_2

This register provides access to various PHY control registers, for control of clocking, group MDIO access, and autonegotiation.

Table 49. Bit Descriptions for PHY_CTRL_2

Bits

Bit Name

Description

Reset

Access

[15:12]

RESERVED

Reserved.

0x0

R/W

DN_SPEED_TO_100_EN

Setting this bit enables downspeed to 100BASE-TX. Note that autonegotiation must

also be enabled. If the PHY is unable to bring a link up at 1000BASE-T, it automatically

drops down to 100BASE-TX (assuming this speed has been advertised). Note that

the default value of this register bit is configurable via the hardware configuration

pins performing the PHY_CFG1 and PHY_CFG0 functions, which allows the default

operation of the PHY to be configured in unmanaged applications.

0x0

R/W

1: enable downspeed to 100BASE-TX.

0: disable downspeed to 100BASE-TX.

DN_SPEED_TO_10_EN

Setting this bit enables downspeed to 10BASE-T. Note that autonegotiation must

also be enabled. If the PHY is unable to bring a link up at a high speed, it automatically

drops down to 10BASE-T (assuming this speed has been advertised) if necessary.

0x0

R/W

1: enable downspeed to 10BASE-T.

0: disable downspeed to 10BASE-T.

[9:7]

RESERVED

Reserved.

0x6

R/W

GROUP_MDIO_EN

The group MDIO enable register bit may be used to place the PHY in group MDIO

mode. In this mode, the PHY responds to any write or address operation to PHY

address 5'd31 as if it was an access to its own PHY address. It is recommended that

this bit be set only when performing specific sequences and then be cleared again.

0x0

R/W

[5:0]

RESERVED

Reserved.

0x8

R/W

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