ADIN1300BCPZ-R7 datasheet(18/79 Pages) AD

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ADIN1300

Data Sheet

Rev. 0 | Page 18 of 79

RMII Interface Mode

MAC

RXD_0 AND RXD_1

CRS_DV

RX_ER

TXD_0 AND TXD_1

TX_EN

REF_CLK

50MHz

REFERENCE

CLOCK

PHY

Figure 23. RMII MAC-PHY Interface Signals

This interface is capable of supporting 10 Mbps and 100 Mbps

data rates. A single 50 MHz reference clock (REF_CLK) is

sourced from the MAC to PHY (or from an external source) to

the XTAL_I/CLK_IN/REF_CLK pin for both the transmit and

receive interfaces.

The receive data (RXD_0 pin and RXD_1 pin), transitions

synchronously to the reference clock (REF_CLK). The carrier

sense/received data valid signal (CRS_DV) is a combination of the

CRS and RX_DV signals and is asserted while the receive medium

is nonidle. The CRS_DV is asserted asynchronously to REF_CLK

and deasserted synchronously. RX_ER is also synchronous to

REF_CLK, and is asserted when an error is detected in the

received frame or when a false carrier is detected in 100BASE-TX.

RX_ER assertion on a false carrier can be disabled by software.

The MAC transmits the TXD_0 pin and TXD_1 pin

synchronously to REF_CLK, and asserts TX_EN to indicate to

the ADIN1300 that transmission data is available on the

TXD_0 pin and TXD_1 pin lines.

AUTONEGOTIATION

The ADIN1300 includes autonegotiation capability in accordance

with IEE 802.3 Clause 28, providing a mechanism for exchanging

information between PHYs to allow link partners to agree to a

common mode of operation at the highest supported speed.

During the autonegotiation process, the PHYs advertise their

own capabilities and compares to those received from the link

partner. The concluded operating mode is the highest speed

capability and duplex setting common across the two devices.

In the event of the link being dropped, the autonegotiation

process restarts automatically.

Autonegotiation can be restarted by request through a write to

the RESTART_ANEG bit field in the MII register.

The autonegotiation process takes some time to complete,

depending on the number of pages exchanged. Clause 28 of the

IEEE 802.3 standard details the timers related to autonegotiation.

Master/Slave Resolution

For 1000BASE-T links, autonegotiation is also used to resolve

master or slave status. The PHY can be configured to prefer

master or slave through the hardware configuration or

manually configured for fixed master or slave through the

MSTR_SLV_CONTROL register, Bit 11 and Bit 12 (MAN_

MSTR_ADV bit and MAN_MSTR_SLV_EN_ADV bit,

respectively). If the user choses to manually fix this configuration,

they must configure each side of the link differently.

Polarity Inversion Correction

The ADIN1300 is capable of detecting if the proper polarity is

present on the cable and adjust the polarity if not. If polarity

inversion has been detected, it is identified in the

PHY_STATUS_1 register (see Table 53).

Automatic MDI Crossover

The ADIN1300 is capable of distinguishing if a straight or

crossover cable is connected between the link partners. The

ADIN1300 automatically detects and sets the MDI configuration

to match its receiver to that of the remote transmitter, thereby

avoiding need for crossover cables or cross-wired cables. Details

on the automatic MDI/MDIX process is included in Clause 40,

Section 40.8.2. This feature is configured through the hardware

strapping configuration (see Table 24) or, alternatively, can be

changed through software access via the MDIO interface.

AUTONEGOTIATION DISABLED

Autonegotiation is always used for a 1000BASE-T link, as

required by the IEEE standards. 10BASE-Te or 100BASE-TX

can use or disable autonegotiation. When autonegotiation is

disabled, the PHY is configured for a single speed and the user

must ensure that both sides of the link are configured properly.

See Table 23 for more details on configuring the device with

autonegotiation enabled or disabled.

If the ADIN1300 has autonegotiation enabled and the other side

of the link has autonegotiation disabled, the ADIN1300 detects

this and parallel detects, as per the IEEE standard, and attempts

to bring up a link at the speed the remote PHY is configured to.

MANAGEMENT INTERFACE

The MII management interface provides a two-wire serial

interface between a host processor or MAC and the ADIN1300,

allowing access to control and status information in the subsystem

and PHY core management registers.

The MII management interface consists of the following:

•

MDC, clock line

•

MDIO, bidirectional data line

•

PHYAD_0 pin to PHYAD_3 pin, which configures device

addresses for each PHY

•

INT_N, management interrupt

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