ADIN1300BCPZ-R7 datasheet(74/79 Pages) AD

74 / 79 page

ADIN1300

Data Sheet

Rev. 0 | Page 74 of 79

Bits

Bit Name

Description

Reset

Access

[8:6]

GE_RGMII_RX_SEL

This field allows the RGMII receive clock delay to be specified in terms of the

data link layer (DLL) unit delay (tU = 200 ps).

0x0

R/W

111: 10 × tU + 400 ps.

110: 9 × tU + 400 ps.

101: reserved.

100: reserved.

011: reserved.

010: 7 × tU + 400 ps.

001: 6 × tU + 400 ps.

000: 8 × tU + 400 ps.

[5:3]

GE_RGMII_GTX_SEL

This field allows the RGMII transmit clock delay to be specified in terms of

the DLL unit delay (tU = 200 ps).

0x0

R/W

111: 10 × tU + 400 ps.

110: 9 × tU + 400 ps.

101: reserved.

100: reserved.

011: reserved.

010: 7 × tU + 400 ps.

001: 6 × tU + 400 ps.

000: 8 × tU + 400 ps.

GE_RGMII_RX_ID_EN

Enable/disable receive clock internal 2 ns delay in RGMII mode. Note that

the default value of this bit is configurable via hardware configuration pins.

This allows the default operation of the PHY to be configured in

unmanaged applications.

0x1

R/W

1: enable receive clock internal 2 ns delay in RGMII mode.

0: disable receive clock internal 2 ns delay in RGMII mode.

GE_RGMII_TX_ID_EN

Enable/disable transmit clock internal 2 ns delay in RGMII mode. Note that

the default value of this bit is configurable via hardware configuration pins.

This allows the default operation of the PHY to be configured in

unmanaged applications.

0x1

R/W

1: enable transmit clock internal 2 ns delay in RGMII mode.

0: disable transmit clock internal 2 ns delay in RGMII mode.

GE_RGMII_EN

This bit selects the RGMII MAC interface mode. Note that the default value

of this bit is configurable via hardware configuration pins. This allows the

default operation of the PHY to be configured in unmanaged applications.

0x1

R/W

Subsystem RMII Configuration Register

Address: 0xFF24, Reset: 0x0116, Name: GE_RMII_CFG

This register allows the MAC interface RMII configuration to be controlled.

Table 120. Bit Descriptions for GE_RMII_CFG

Bits

Bit Name

Description

Reset

Access

[15:8]

RESERVED

Reserved.

0x1

GE_RMII_FIFO_RST

This bit allows the RMII FIFO to be reset.

0x0

R/W

[6:4]

GE_RMII_FIFO_DPTH

This field allows the RMII receive FIFO depth to be selected.

0x1

R/W

111: reserved.

110: reserved.

101: ± 24 bits.

100: ± 20 bits.

011: ± 16 bits.

010: ± 12 bits.

001: ± 8 bits.

000: ± 4 bits.

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