MC9328MXL datasheet(16/84 Pages) FREESCALE

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MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor

Specifications

3.7 DPLL Timing Specifications

Parameters of the DPLL are given in Table 10. In this table, Tref is a reference clock period after the

pre-divider and Tdck is the output double clock period.

Table 10. DPLL Specifications

Parameter

Test Conditions

Minimum

Typical

Maximum

Unit

Reference clock freq range

Vcc = 1.8V

–

100

MHz

Pre-divider output clock

freq range

Vcc = 1.8V

–

MHz

Double clock freq range

Vcc = 1.8V

–

220

MHz

Pre-divider factor (PD)

–

Total multiplication factor (MF)

Includes both integer

and fractional parts

5–

–

MF integer part

–

MF numerator

Should be less than the

denominator

–

1022

–

MF denominator

–

1023

–

Pre-multiplier lock-in time

–

312.5

µsec

Freq lock-in time after

full reset

FOL mode for non-integer MF

(does not include pre-multi lock-in

time)

250

280

(56

µs)

300

Tref

Freq lock-in time after

partial reset

FOL mode for non-integer MF

(does not include pre-multi lock-in

time)

220

250

(50

µs)

270

Tref

Phase lock-in time after

full reset

FPL mode and integer MF (does

not include pre-multi lock-in time)

300

350

(70

µs)

400

Tref

Phase lock-in time after

partial reset

FPL mode and integer MF (does

not include pre-multi lock-in time)

270

320

(64

µs)

370

Tref

Freq jitter (p-p)

–

0.005

(0.01%)

0.01

2•Tdck

Phase jitter (p-p)

Integer MF, FPL mode, Vcc=1.8V

–

1.0

(10%)

1.5

Power supply voltage

–

1.7

–

2.5

Power dissipation

FOL mode, integer MF,

fdck = 200 MHz, Vcc = 1.8V

––

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