MC9328MXL datasheet(14/84 Pages) FREESCALE

14 / 84 page

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor

Specifications

3.6 Embedded Trace Macrocell

All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the

ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit

shift register comprised of the following:

•

32-bit data field

•

7-bit address field

•

A read/write bit

The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address

field, and a 1 into the read/write bit.

A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit

data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.

The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used

in Figure 2.

Figure 2. Trace Port Timing Diagram

EXTAL32k startup time

800

–

EXTAL16M input jitter (peak to peak)

–

TBD

–

EXTAL16M startup time

TBD

–

Table 9. Trace Port Timing Diagram Parameter Table

Ref

No.

Parameter

1.8V ± 0.10V

3.0V ± 0.30V

Unit

Minimum

Maximum

Minimum

Maximum

CLK frequency

100

MHz

Clock high time

1.3

–

Clock low time

–

Table 8. 32k/16M Oscillator Signal Timing (Continued)

Parameter

Minimum

RMS

Maximum

Unit

TRACECLK

Output Trace Port

Valid Data

TRACECLK

(Half-Rate Clocking Mode)

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