MC9328MXL datasheet(46/84 Pages) FREESCALE

46 / 84 page

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor

Specifications

3.10 SPI Timing Diagrams

To utilize the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as

a master, two control signals are used for data transfer rate control: the SS signal (output) and the

SPI_RDY signal (input). The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2

Sample Period Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for

either SPI 1 or SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI 1

Control Register (CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS

becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as

well as to increment the data FIFO. Figure 31 through Figure 35 show the timing relationship of the master

SPI using different triggering mechanisms.

Figure 31. Master SPI Timing Diagram Using SPI_RDY Edge Trigger

Figure 32. Master SPI Timing Diagram Using SPI_RDY Level Trigger

Figure 33. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger

Figure 34. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT

SPIRDY

SCLK, MOSI, MISO

SPIRDY

SCLK, MOSI, MISO

SS (output)

SS (input)

SCLK, MOSI, MISO

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