MC9328MXL datasheet(57/84 Pages) FREESCALE

57 / 84 page

Specifications

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor

Figure 44. SDIO IRQ Timing Diagram

ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In

this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the

clock running, and allows the user to submit commands as normal. After all commands are submitted, the

user can switch back to the data transfer operation and all counter and status values are resumed as access

continues.

Figure 45. SDIO ReadWait Timing Diagram

3.13 Memory Stick Host Controller

The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS,

MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in

either four-state or two-state access mode.

The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according

to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet

transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1,

BS2, and BS3 states are regarded as one packet length and one communication transfer is always

completed within one packet length (in four-state access mode).

The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When

an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0

and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.

Interrupt Period

IRQ

DAT[1]

For 4-bit

L H

Interrupt Period

DAT[1]

For 1-bit

CMD

Content

S T

E Z Z P

E Z Z

******

Z Z

Response

CRC

Block Data

DAT[1]

For 4-bit

DAT[2]

For 4-bit

CMD

******

P S T

E Z Z

******

CMD52

CRC

E Z Z

Block Data

L L L L L L L L L L L L L L L L L L L L L H Z S

Block Data

Z Z L H

Block Data

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