MC9328MXL datasheet(50/84 Pages) FREESCALE

50 / 84 page

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor

Specifications

3.12 Multimedia Card/Secure Digital Host Controller

The DMA interface block controls all data routing between the external data bus (DMA access), internal

MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that

monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the

MMC/SD module (inner system) and the application (user programming).

Figure 38. Chip-Select Read Cycle Timing Diagram

Table 18. SDHC Bus Timing Parameter Table

Ref

No.

Parameter

1.8V ± 0.10V

3.0 ± 0.30V

Unit

Minimum

Maximum

Minimum

Maximum

CLK frequency at Data transfer Mode

(PP)1—10/30 cards

CL ≤ 100 pF / 250 pF (10/30 cards)

25/5

MHz

CLK frequency at Identification Mode2

CL ≤ 250 pF (21 cards)

400

kHz

Clock high time1—10/30 cards

6/33

–

10/50

–

Clock low time1—10/30 cards

15/75

–

10/50

–

Clock fall time1—10/30 cards

–

10/50

(5.00)3

–

10/50

Clock rise time1—10/30 cards

–

14/67

(6.67)3

–

10/50

Input hold time3—10/30 cards

CL ≤ 25 pF (1 card)

5.7/5.7

–

5/5

–

Input setup time3—10/30 cards

5.7/5.7

–

5/5

–

Output hold time3—10/30 cards

5.7/5.7

–

5/5

–

Output setup time3—10/30 cards

5.7/5.7

–

5/5

–

Output delay time3

Bus Clock

CMD_DAT Input

CMD_DAT Output

Valid Data

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