MC9328MXL datasheet(78/84 Pages) FREESCALE

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MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor

Specifications

Figure 62. Sensor Output Data on Pixel Clock Rising Edge

CSI Latches Data on Pixel Clock Falling Edge

The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and

setup time, according to:

max rise time allowed = (positive duty cycle - hold time)

max fall time allowed = (negative duty cycle - setup time)

In most of case, duty cycle is 50 / 50, therefore:

max rise time = (period / 2 - hold time)

max fall time = (period / 2 - setup time)

For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.

positive duty cycle = 10 / 2 = 5ns

=> max rise time allowed = 5 - 1 = 4ns

negative duty cycle = 10 / 2 = 5ns

=> max fall time allowed = 5 - 1 = 4ns

Falling-edge latch data

max fall time allowed = (negative duty cycle - hold time)

max rise time allowed = (positive duty cycle - setup time)

Table 32. Non-Gated Clock Mode Parameters

Ref No.

Parameter

Min

Max

Unit

csi_vsync to csi_pixclk

180

–

csi_d setup time

–

csi_d hold time

–

csi_pixclk high time

10.42

–

csi_pixclk low time

10.42

–

csi_pixclk frequency

MHz

VSYNC

PIXCLK

DATA[7:0]

Valid Data

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