MC9328MXL datasheet(60/84 Pages) FREESCALE

60 / 84 page

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor

Specifications

3.14 Pulse-Width Modulator

The PWM can be programmed to select one of two clock signals as its source frequency. The selected

clock signal is passed through a divider and a prescaler before being input to the counter. The output is

available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in

Figure 47 and the parameters are listed in Table 22.

Figure 47. PWM Output Timing Diagram

3.15 SDRAM Controller

A write to an address within the memory region initiates the program sequence. The first command issued

to the SyncFlash is Load Command Register. The value in A [7:0] determines which operation the

command performs. For this write setup operation, an address of 0x40 is hardware generated. The bank

and other address lines are driven with the address to be programmed. The next command is Active which

registers the row address and confirms the bank address. The third command supplies the column address,

re-confirms the bank address, and supplies the data to be written. SyncFlash does not support burst writes,

therefore a Burst Terminate command is not required.

A read to the memory region initiates the status read sequence. The first command issued to the SyncFlash

is the Load Command Register with A [7:0] set to 0x70 which corresponds to the Read Status Register

operation. The bank and other address lines are driven to the selected address. The second command is

Table 22. PWM Output Timing Parameter Table

Ref

No.

Parameter

1.8V ± 0.10V

3.0V ± 0.30V

Unit

Minimum

Maximum

Minimum

Maximum

System CLK frequency1

CL of PWMO = 30 pF

0870

100

MHz

Clock high time1

3.3

–

5/10

–

Clock low time1

7.5

–

5/10

–

Clock fall time1

–5

–

5/10

Clock rise time1

–

6.67–5/10

Output delay time1

5.7

–

Output setup time1

5.7

–

System Clock

PWM Output

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