MC9328MXL datasheet(56/84 Pages) FREESCALE

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MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor

Specifications

3.12.2 SDIO-IRQ and ReadWait Service Handling

In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the

interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data

in this mode. The memory controller generates an interrupt according to this low and the system interrupt

continues until the source is removed (SD_DAT[1] returns to its high level).

In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the "Interrupt

Period" during the data access, and the controller must sample SD_DAT[1] during this short period to

determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each

block (512 bytes).

Table 20. Timing Values for Figure 39 through Figure 43

Parameter

Symbol

Minimum

Maximum

Unit

Parameter

MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum

(VIL)

MMC/SD bus clock, CLK

(All values are referred to

minimum (VIH) and

maximum (VIL)

Command response cycle

NCR

Clock

cycles

Command response cycle

Identification response cycle

NID

Clock

cycles

Identification response

cycle

Access time delay cycle

NAC

TAAC + NSAC

Clock

cycles

Access time delay cycle

Command read cycle

NRC

–

Clock

cycles

Command read cycle

Command-command cycle

NCC

–

Clock

cycles

Command-command cycle

Command write cycle

NWR

–

Clock

cycles

Command write cycle

Stop transmission cycle

NST

Clock

cycles

Stop transmission cycle

TAAC: Data read access time -1 defined in CSD register bit[119:112]

NSAC: Data read access time -2 in CLK cycles (NSAC·100) defined in CSD register

bit[111:104]

TAAC: Data read access

time -1 defined in CSD

NSAC: Data read access

time -2 in CLK cycles

(NSAC·100) defined in

CSD register bit[111:104]

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