MC9328MXL datasheet(51/84 Pages) FREESCALE

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Specifications

MC9328MXL Advance Information, Rev. 5

Freescale Semiconductor

3.12.1 Command Response Timing on MMC/SD Bus

The card identification and card operation conditions timing are processed in open-drain mode. The card

response to the host command starts after exactly NID clock cycles. For the card address assignment,

SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and

card response is NCR clock cycles as illustrated in Figure 39. The symbols for Figure 39 through Figure 43

are defined in Table 19.

Figure 39. Timing Diagrams at Identification Mode

After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in

Figure 40, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a

period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the

responding card. The other two diagrams show the separating periods NRC and NCC.

Table 19. State Signal Parameters for Figure 39 through Figure 43

Card Active

Host Active

Symbol

Definition

Symbol

Definition

High impedance state

Start bit (0)

Data bits

Transmitter bit

(Host = 1, Card = 0)

Repetition

One-cycle pull-up (1)

CRC

Cyclic redundancy check bits (7 bits)

End bit (1)

SET_RCA Timing

Identification Timing

Host Command

CID/OCR

NID cycles

CMD

Content

S T

E Z

Z S T

Content

Z Z

******

CRC

Host Command

CID/OCR

NCR cycles

CMD

Content

S T

E Z

Z S T

Content

Z Z

******

CRC

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